Index: llvm/include/llvm/CodeGen/TargetLowering.h
===================================================================
--- llvm/include/llvm/CodeGen/TargetLowering.h
+++ llvm/include/llvm/CodeGen/TargetLowering.h
@@ -453,6 +453,12 @@
     return false;
   }
 
+  /// Return true if instruction generated for ICMP_EQ could be folded with
+  /// instruction generated for ICMP_S(G|L)T
+  virtual bool isICMP_EQFoldedWithICMP_ST() const {
+    return true;
+  }
+
   /// Return true if it is safe to transform an integer-domain bitwise operation
   /// into the equivalent floating-point operation. This should be set to true
   /// if the target has IEEE-754-compliant fabs/fneg operations for the input
Index: llvm/lib/CodeGen/CodeGenPrepare.cpp
===================================================================
--- llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -1412,6 +1412,68 @@
   return MadeChange;
 }
 
+static bool foldICmpWithDominatingICmp(CmpInst *Cmp, const TargetLowering &TLI) {
+  if (TLI.isICMP_EQFoldedWithICMP_ST())
+    return false;
+
+  ICmpInst::Predicate Pred = Cmp->getPredicate();
+  if (Pred != ICmpInst::ICMP_EQ)
+    return false;
+
+  Value *X = Cmp->getOperand(0), *Y = Cmp->getOperand(1);
+  const APInt *C;
+  if (!match(Y, m_APInt(C)))
+    return false;
+
+  for (User *U : Cmp->users()) {
+    if (isa<BranchInst>(U) && cast<BranchInst>(U)->isConditional())
+      continue;
+    if (isa<SelectInst>(U) && cast<SelectInst>(U)->getCondition() == Cmp)
+      continue;
+    return false;
+  }
+
+  BasicBlock *CmpBB = Cmp->getParent();
+  BasicBlock *DomBB = CmpBB->getSinglePredecessor();
+  if (!DomBB)
+    return false;
+
+  Value *DomCond;
+  BasicBlock *TrueBB, *FalseBB;
+  if (!match(DomBB->getTerminator(), m_Br(m_Value(DomCond), TrueBB, FalseBB)))
+    return false;
+
+  ICmpInst::Predicate DomPred;
+  if (!match(DomCond, m_ICmp(DomPred, m_Specific(X), m_Specific(Y))))
+    return false;
+  if (DomPred != ICmpInst::ICMP_SGT && DomPred != ICmpInst::ICMP_SLT)
+    return false;
+
+  ICmpInst::Predicate newPred =
+      DomPred == ICmpInst::ICMP_SGT ? ICmpInst::ICMP_SLT
+                                    : ICmpInst::ICMP_SGT;
+
+  for (User *U : Cmp->users()) {
+    if (auto *BI = dyn_cast<BranchInst>(U)) {
+      assert(BI->isConditional() && "Must be conditional");
+      BI->swapSuccessors();
+      continue;
+    }
+    if (auto *SI = dyn_cast<SelectInst>(U)) {
+      // Swap operands
+      Value *TrueValue = SI->getTrueValue();
+      Value *FalseValue = SI->getFalseValue();
+      SI->setTrueValue(FalseValue);
+      SI->setFalseValue(TrueValue);
+      SI->swapProfMetadata();
+      continue;
+    }
+    llvm_unreachable("Must be a branch or a select");
+  }
+  Cmp->setPredicate(newPred);
+  return true;
+}
+
 bool CodeGenPrepare::optimizeCmp(CmpInst *Cmp, bool &ModifiedDT) {
   if (sinkCmpExpression(Cmp, *TLI))
     return true;
@@ -1422,6 +1484,9 @@
   if (combineToUSubWithOverflow(Cmp, ModifiedDT))
     return true;
 
+  if (foldICmpWithDominatingICmp(Cmp, *TLI))
+    return true;
+
   return false;
 }
 
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -615,6 +615,10 @@
       return true;
     }
 
+    bool isICMP_EQFoldedWithICMP_ST() const override {
+      return false;
+    }
+
     bool hasAndNotCompare(SDValue) const override {
       return true;
     }
Index: llvm/test/CodeGen/PowerPC/use-cr-result-of-dom-icmp-st.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/use-cr-result-of-dom-icmp-st.ll
@@ -0,0 +1,1149 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O3 < %s | FileCheck %s -check-prefix=PPC64LE
+
+; Test cases are generated from:
+; long long NAME(PARAM a, PARAM b) {
+;   if (LHS > RHS)
+;     return b;
+;   if (LHS < RHS)
+;     return a;\
+;   return a * b;
+; }
+; Please note funtion name is defined as <PARAM>_<LHS>_<RHS>. Take ll_a_op_b__1
+; for example. ll is PARAM, a_op_b (i.e., a << b) is LHS, _1 (i.e., -1) is RHS.
+
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+define i64 @ll_a_b(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ll_a_b:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    cmpd 3, 4
+; PPC64LE-NEXT:    ble 0, .LBB0_2
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    mr 3, 4
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .LBB0_2: # %if.end
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 5, 4, 0
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp slt i64 %a, %b
+  %mul = select i1 %cmp1, i64 1, i64 %b
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_LLONG_MIN(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ll_a_op_b_LLONG_MIN:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    sld 6, 3, 4
+; PPC64LE-NEXT:    sldi 7, 5, 63
+; PPC64LE-NEXT:    cmpld 6, 7
+; PPC64LE-NEXT:    isel 3, 3, 5, 2
+; PPC64LE-NEXT:    mulld 3, 3, 4
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp eq i64 %shl, -9223372036854775808
+  %mul = select i1 %cmp, i64 %a, i64 1
+  %retval.0 = mul nsw i64 %mul, %b
+  ret i64 %retval.0
+}
+
+define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ll_a_op_b__2:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    sld 5, 3, 4
+; PPC64LE-NEXT:    cmpdi 5, -2
+; PPC64LE-NEXT:    ble 0, .LBB2_2
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    mr 3, 4
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .LBB2_2: # %if.end
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 5, 4, 0
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, -2
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ll_a_op_b__1:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    sld 5, 3, 4
+; PPC64LE-NEXT:    cmpdi 5, -1
+; PPC64LE-NEXT:    ble 0, .LBB3_2
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    mr 3, 4
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .LBB3_2: # %if.end
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 5, 4, 0
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, -1
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_0(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ll_a_op_b_0:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    sld. 5, 3, 4
+; PPC64LE-NEXT:    ble 0, .LBB4_2
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    mr 3, 4
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .LBB4_2: # %if.end
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 5, 4, 0
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 0
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ll_a_op_b_1:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    sld 5, 3, 4
+; PPC64LE-NEXT:    cmpdi 5, 1
+; PPC64LE-NEXT:    ble 0, .LBB5_2
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    mr 3, 4
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .LBB5_2: # %if.end
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 5, 4, 0
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 1
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_2(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ll_a_op_b_2:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    sld 5, 3, 4
+; PPC64LE-NEXT:    cmpdi 5, 2
+; PPC64LE-NEXT:    ble 0, .LBB6_2
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    mr 3, 4
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .LBB6_2: # %if.end
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 5, 4, 0
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 2
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_LLONG_MAX(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ll_a_op_b_LLONG_MAX:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    li 5, -2
+; PPC64LE-NEXT:    sld 6, 3, 4
+; PPC64LE-NEXT:    rldicr 5, 5, 63, 63
+; PPC64LE-NEXT:    cmpld 6, 5
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 4, 5, 2
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i64 %a, %b
+  %cmp2 = icmp eq i64 %shl, 9223372036854775807
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %retval.0 = mul nsw i64 %mul, %a
+  ret i64 %retval.0
+}
+
+define i64 @ll_a_LLONG_MIN(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ll_a_LLONG_MIN:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    sldi 6, 5, 63
+; PPC64LE-NEXT:    cmpld 3, 6
+; PPC64LE-NEXT:    isel 3, 6, 5, 2
+; PPC64LE-NEXT:    mulld 3, 3, 4
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, -9223372036854775808
+  %mul = select i1 %cmp, i64 -9223372036854775808, i64 1
+  %retval.0 = mul nsw i64 %mul, %b
+  ret i64 %retval.0
+}
+
+define i64 @ll_a__2(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ll_a__2:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    cmpdi 3, -2
+; PPC64LE-NEXT:    ble 0, .LBB9_2
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    mr 3, 4
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .LBB9_2: # %if.end
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 5, 4, 0
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, -2
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a__1(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ll_a__1:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    cmpdi 3, -1
+; PPC64LE-NEXT:    ble 0, .LBB10_2
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    mr 3, 4
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .LBB10_2: # %if.end
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 5, 4, 0
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, -1
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_0(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ll_a_0:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    cmpdi 3, 0
+; PPC64LE-NEXT:    ble 0, .LBB11_2
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    mr 3, 4
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .LBB11_2: # %if.end
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 5, 4, 0
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, 0
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_1(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ll_a_1:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    cmpdi 3, 1
+; PPC64LE-NEXT:    ble 0, .LBB12_2
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    mr 3, 4
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .LBB12_2: # %if.end
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 5, 4, 0
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, 1
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_2(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ll_a_2:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    cmpdi 3, 2
+; PPC64LE-NEXT:    ble 0, .LBB13_2
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    mr 3, 4
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .LBB13_2: # %if.end
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 5, 4, 0
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, 2
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_LLONG_MAX(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ll_a_LLONG_MAX:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    li 5, -2
+; PPC64LE-NEXT:    rldicr 5, 5, 63, 63
+; PPC64LE-NEXT:    cmpld 3, 5
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 4, 5, 2
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp1 = icmp eq i64 %a, 9223372036854775807
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %retval.0 = mul nsw i64 %mul, %a
+  ret i64 %retval.0
+}
+
+define i64 @i_a_b(i32 signext %a, i32 signext %b) {
+; PPC64LE-LABEL: i_a_b:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmpw 3, 4
+; PPC64LE-NEXT:    isel 5, 5, 4, 0
+; PPC64LE-NEXT:    mullw 3, 5, 3
+; PPC64LE-NEXT:    isel 3, 4, 3, 1
+; PPC64LE-NEXT:    extsw 3, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp slt i32 %a, %b
+  %mul = select i1 %cmp1, i32 1, i32 %b
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_INT_MIN(i32 signext %a, i32 signext %b) {
+; PPC64LE-LABEL: i_a_op_b_INT_MIN:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    slw 6, 3, 4
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    xoris 6, 6, 32768
+; PPC64LE-NEXT:    cmplwi 6, 0
+; PPC64LE-NEXT:    isel 3, 3, 5, 2
+; PPC64LE-NEXT:    mullw 3, 3, 4
+; PPC64LE-NEXT:    extsw 3, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp eq i32 %shl, -2147483648
+  %mul = select i1 %cmp, i32 %a, i32 1
+  %retval.0.in = mul nsw i32 %mul, %b
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) {
+; PPC64LE-LABEL: i_a_op_b__2:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    slw 6, 3, 4
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmpwi 6, -2
+; PPC64LE-NEXT:    isel 5, 5, 4, 0
+; PPC64LE-NEXT:    mullw 3, 5, 3
+; PPC64LE-NEXT:    isel 3, 4, 3, 1
+; PPC64LE-NEXT:    extsw 3, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, -2
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) {
+; PPC64LE-LABEL: i_a_op_b__1:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    slw 6, 3, 4
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmpwi 6, -1
+; PPC64LE-NEXT:    isel 5, 5, 4, 0
+; PPC64LE-NEXT:    mullw 3, 5, 3
+; PPC64LE-NEXT:    isel 3, 4, 3, 1
+; PPC64LE-NEXT:    extsw 3, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, -1
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_0(i32 signext %a, i32 signext %b) {
+; PPC64LE-LABEL: i_a_op_b_0:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    slw 6, 3, 4
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmpwi 6, 0
+; PPC64LE-NEXT:    isel 5, 5, 4, 0
+; PPC64LE-NEXT:    mullw 3, 5, 3
+; PPC64LE-NEXT:    isel 3, 4, 3, 1
+; PPC64LE-NEXT:    extsw 3, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 0
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) {
+; PPC64LE-LABEL: i_a_op_b_1:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    slw 6, 3, 4
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmpwi 6, 1
+; PPC64LE-NEXT:    isel 5, 5, 4, 0
+; PPC64LE-NEXT:    mullw 3, 5, 3
+; PPC64LE-NEXT:    isel 3, 4, 3, 1
+; PPC64LE-NEXT:    extsw 3, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 1
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) {
+; PPC64LE-LABEL: i_a_op_b_2:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    slw 6, 3, 4
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmpwi 6, 2
+; PPC64LE-NEXT:    isel 5, 5, 4, 0
+; PPC64LE-NEXT:    mullw 3, 5, 3
+; PPC64LE-NEXT:    isel 3, 4, 3, 1
+; PPC64LE-NEXT:    extsw 3, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 2
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_INT_MAX(i32 signext %a, i32 signext %b) {
+; PPC64LE-LABEL: i_a_op_b_INT_MAX:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    slw 6, 3, 4
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    xoris 6, 6, 32767
+; PPC64LE-NEXT:    cmplwi 6, 65535
+; PPC64LE-NEXT:    isel 4, 4, 5, 2
+; PPC64LE-NEXT:    mullw 3, 4, 3
+; PPC64LE-NEXT:    extsw 3, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i32 %a, %b
+  %cmp2 = icmp eq i32 %shl, 2147483647
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %retval.0.in = mul nsw i32 %mul, %a
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_INT_MIN(i32 signext %a, i32 signext %b) {
+; PPC64LE-LABEL: i_a_INT_MIN:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    xoris 3, 3, 32768
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmplwi 3, 0
+; PPC64LE-NEXT:    lis 3, -32768
+; PPC64LE-NEXT:    isel 3, 3, 5, 2
+; PPC64LE-NEXT:    mullw 3, 3, 4
+; PPC64LE-NEXT:    extsw 3, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, -2147483648
+  %mul = select i1 %cmp, i32 -2147483648, i32 1
+  %retval.0.in = mul nsw i32 %mul, %b
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a__2(i32 signext %a, i32 signext %b) {
+; PPC64LE-LABEL: i_a__2:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmpwi 3, -2
+; PPC64LE-NEXT:    isel 5, 5, 4, 0
+; PPC64LE-NEXT:    mullw 3, 5, 3
+; PPC64LE-NEXT:    isel 3, 4, 3, 1
+; PPC64LE-NEXT:    extsw 3, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, -2
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a__1(i32 signext %a, i32 signext %b) {
+; PPC64LE-LABEL: i_a__1:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmpwi 3, -1
+; PPC64LE-NEXT:    isel 5, 5, 4, 0
+; PPC64LE-NEXT:    mullw 3, 5, 3
+; PPC64LE-NEXT:    isel 3, 4, 3, 1
+; PPC64LE-NEXT:    extsw 3, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, -1
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_0(i32 signext %a, i32 signext %b) {
+; PPC64LE-LABEL: i_a_0:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmpwi 3, 0
+; PPC64LE-NEXT:    isel 5, 5, 4, 0
+; PPC64LE-NEXT:    mullw 3, 5, 3
+; PPC64LE-NEXT:    isel 3, 4, 3, 1
+; PPC64LE-NEXT:    extsw 3, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, 0
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_1(i32 signext %a, i32 signext %b) {
+; PPC64LE-LABEL: i_a_1:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmpwi 3, 1
+; PPC64LE-NEXT:    isel 5, 5, 4, 0
+; PPC64LE-NEXT:    mullw 3, 5, 3
+; PPC64LE-NEXT:    isel 3, 4, 3, 1
+; PPC64LE-NEXT:    extsw 3, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, 1
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_2(i32 signext %a, i32 signext %b) {
+; PPC64LE-LABEL: i_a_2:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmpwi 3, 2
+; PPC64LE-NEXT:    isel 5, 5, 4, 0
+; PPC64LE-NEXT:    mullw 3, 5, 3
+; PPC64LE-NEXT:    isel 3, 4, 3, 1
+; PPC64LE-NEXT:    extsw 3, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, 2
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_INT_MAX(i32 signext %a, i32 signext %b) {
+; PPC64LE-LABEL: i_a_INT_MAX:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    xoris 6, 3, 32767
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmplwi 6, 65535
+; PPC64LE-NEXT:    isel 4, 4, 5, 2
+; PPC64LE-NEXT:    mullw 3, 4, 3
+; PPC64LE-NEXT:    extsw 3, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp1 = icmp eq i32 %a, 2147483647
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %retval.0.in = mul nsw i32 %mul, %a
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @ull_a_b(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ull_a_b:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    cmpld 3, 4
+; PPC64LE-NEXT:    ble 0, .LBB30_2
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    mr 3, 4
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .LBB30_2: # %if.end
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 5, 4, 0
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp ult i64 %a, %b
+  %mul = select i1 %cmp1, i64 1, i64 %b
+  %spec.select = mul i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ull_a_op_b_0(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ull_a_op_b_0:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    sld. 5, 3, 4
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 3, 3, 5, 2
+; PPC64LE-NEXT:    mulld 3, 3, 4
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp eq i64 %shl, 0
+  %mul = select i1 %cmp, i64 %a, i64 1
+  %retval.0 = mul i64 %mul, %b
+  ret i64 %retval.0
+}
+
+define i64 @ull_a_op_b_1(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ull_a_op_b_1:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    sld 5, 3, 4
+; PPC64LE-NEXT:    cmpldi 5, 1
+; PPC64LE-NEXT:    ble 0, .LBB32_2
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    mr 3, 4
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .LBB32_2: # %if.end
+; PPC64LE-NEXT:    cmpldi 5, 0
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 5, 4, 2
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp ugt i64 %shl, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 0
+  %mul = select i1 %cmp2, i64 1, i64 %b
+  %spec.select = mul i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ull_a_op_b_2(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ull_a_op_b_2:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    sld 5, 3, 4
+; PPC64LE-NEXT:    cmpldi 5, 2
+; PPC64LE-NEXT:    ble 0, .LBB33_2
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    mr 3, 4
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .LBB33_2: # %if.end
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 4, 5, 2
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp ugt i64 %shl, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 2
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ull_a_op_b_ULLONG_MAX(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ull_a_op_b_ULLONG_MAX:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    sld 6, 3, 4
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmpdi 6, -1
+; PPC64LE-NEXT:    isel 4, 4, 5, 2
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i64 %a, %b
+  %cmp2 = icmp eq i64 %shl, -1
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %retval.0 = mul i64 %mul, %a
+  ret i64 %retval.0
+}
+
+define i64 @ull_a_0(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ull_a_0:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    cmpldi 3, 0
+; PPC64LE-NEXT:    isel 3, 0, 4, 2
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %retval.0 = select i1 %cmp, i64 0, i64 %b
+  ret i64 %retval.0
+}
+
+define i64 @ull_a_1(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ull_a_1:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    cmpldi 3, 1
+; PPC64LE-NEXT:    ble 0, .LBB36_2
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    mr 3, 4
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .LBB36_2: # %if.end
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %mul = mul i64 %b, %a
+  ret i64 %mul
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ull_a_2(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ull_a_2:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    cmpldi 3, 2
+; PPC64LE-NEXT:    ble 0, .LBB37_2
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    mr 3, 4
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .LBB37_2: # %if.end
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 4, 4, 5, 2
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, 2
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ull_a_ULLONG_MAX(i64 %a, i64 %b) {
+; PPC64LE-LABEL: ull_a_ULLONG_MAX:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmpdi 3, -1
+; PPC64LE-NEXT:    isel 4, 4, 5, 2
+; PPC64LE-NEXT:    mulld 3, 4, 3
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp1 = icmp eq i64 %a, -1
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %retval.0 = mul i64 %mul, %a
+  ret i64 %retval.0
+}
+
+define i64 @ui_a_b(i32 zeroext %a, i32 zeroext %b) {
+; PPC64LE-LABEL: ui_a_b:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmplw 3, 4
+; PPC64LE-NEXT:    isel 5, 5, 4, 0
+; PPC64LE-NEXT:    mullw 3, 5, 3
+; PPC64LE-NEXT:    isel 3, 4, 3, 1
+; PPC64LE-NEXT:    clrldi 3, 3, 32
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp ult i32 %a, %b
+  %mul = select i1 %cmp1, i32 1, i32 %b
+  %spec.select = mul i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = zext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @ui_a_op_b_0(i32 zeroext %a, i32 zeroext %b) {
+; PPC64LE-LABEL: ui_a_op_b_0:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    slw. 5, 3, 4
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    isel 3, 3, 5, 2
+; PPC64LE-NEXT:    mullw 3, 3, 4
+; PPC64LE-NEXT:    clrldi 3, 3, 32
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp eq i32 %shl, 0
+  %mul = select i1 %cmp, i32 %a, i32 1
+  %retval.0.in = mul i32 %mul, %b
+  %retval.0 = zext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @ui_a_op_b_1(i32 zeroext %a, i32 zeroext %b) {
+; PPC64LE-LABEL: ui_a_op_b_1:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    slw. 5, 3, 4
+; PPC64LE-NEXT:    li 6, 1
+; PPC64LE-NEXT:    isel 6, 6, 4, 2
+; PPC64LE-NEXT:    cmplwi 5, 1
+; PPC64LE-NEXT:    mullw 3, 6, 3
+; PPC64LE-NEXT:    isel 3, 4, 3, 1
+; PPC64LE-NEXT:    clrldi 3, 3, 32
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp ugt i32 %shl, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 0
+  %mul = select i1 %cmp2, i32 1, i32 %b
+  %spec.select = mul i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = zext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @ui_a_op_b_2(i32 zeroext %a, i32 zeroext %b) {
+; PPC64LE-LABEL: ui_a_op_b_2:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    slw 6, 3, 4
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmplwi 6, 2
+; PPC64LE-NEXT:    isel 5, 4, 5, 2
+; PPC64LE-NEXT:    mullw 3, 5, 3
+; PPC64LE-NEXT:    isel 3, 4, 3, 1
+; PPC64LE-NEXT:    clrldi 3, 3, 32
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp ugt i32 %shl, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 2
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = zext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @ui_a_op_b_UINT_MAX(i32 zeroext %a, i32 zeroext %b) {
+; PPC64LE-LABEL: ui_a_op_b_UINT_MAX:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    slw 6, 3, 4
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmpwi 6, -1
+; PPC64LE-NEXT:    isel 4, 4, 5, 2
+; PPC64LE-NEXT:    mullw 3, 4, 3
+; PPC64LE-NEXT:    clrldi 3, 3, 32
+; PPC64LE-NEXT:    blr
+entry:
+  %shl = shl i32 %a, %b
+  %cmp2 = icmp eq i32 %shl, -1
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %retval.0.in = mul i32 %mul, %a
+  %retval.0 = zext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @ui_a_0(i32 zeroext %a, i32 zeroext %b) {
+; PPC64LE-LABEL: ui_a_0:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    cmplwi 0, 3, 0
+; PPC64LE-NEXT:    isel 3, 0, 4, 2
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %retval.0.in = select i1 %cmp, i32 0, i32 %b
+  %retval.0 = zext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @ui_a_1(i32 zeroext %a, i32 zeroext %b) {
+; PPC64LE-LABEL: ui_a_1:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    cmplwi 0, 3, 0
+; PPC64LE-NEXT:    isel 3, 0, 4, 2
+; PPC64LE-NEXT:    blr
+entry:
+  %0 = icmp eq i32 %a, 0
+  %spec.select = select i1 %0, i32 0, i32 %b
+  %retval.0 = zext i32 %spec.select to i64
+  ret i64 %retval.0
+}
+
+define i64 @ui_a_2(i32 zeroext %a, i32 zeroext %b) {
+; PPC64LE-LABEL: ui_a_2:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmplwi 3, 2
+; PPC64LE-NEXT:    isel 5, 4, 5, 2
+; PPC64LE-NEXT:    mullw 3, 5, 3
+; PPC64LE-NEXT:    isel 3, 4, 3, 1
+; PPC64LE-NEXT:    clrldi 3, 3, 32
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, 2
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = zext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @ui_a_UINT_MAX(i32 zeroext %a, i32 zeroext %b) {
+; PPC64LE-LABEL: ui_a_UINT_MAX:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    li 5, 1
+; PPC64LE-NEXT:    cmpwi 3, -1
+; PPC64LE-NEXT:    isel 4, 4, 5, 2
+; PPC64LE-NEXT:    mullw 3, 4, 3
+; PPC64LE-NEXT:    clrldi 3, 3, 32
+; PPC64LE-NEXT:    blr
+entry:
+  %cmp1 = icmp eq i32 %a, -1
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %retval.0.in = mul i32 %mul, %a
+  %retval.0 = zext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}