Index: lib/Target/AArch64/AArch64CallingConvention.td
===================================================================
--- lib/Target/AArch64/AArch64CallingConvention.td
+++ lib/Target/AArch64/AArch64CallingConvention.td
@@ -303,6 +303,10 @@
                                                D8, D9, D10, D11,
                                                D12, D13, D14, D15)>;
 
+// Non-POD structs are returned in X0.
+def CSR_Win_AArch64_SRet_AAPCS : CalleeSavedRegs<(add CSR_Win_AArch64_AAPCS,
+                                                  X0)>;
+
 // AArch64 PCS for vector functions (VPCS)
 // must (additionally) preserve full Q8-Q23 registers
 def CSR_AArch64_AAVPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22,
Index: lib/Target/AArch64/AArch64RegisterInfo.cpp
===================================================================
--- lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -42,8 +42,14 @@
 const MCPhysReg *
 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   assert(MF && "Invalid MachineFunction pointer.");
-  if (MF->getSubtarget<AArch64Subtarget>().isTargetWindows())
+  if (MF->getSubtarget<AArch64Subtarget>().isTargetWindows()) {
+    if (MF->getFunction().getAttributes().
+        hasAttrSomewhere(Attribute::StructRet))
+      if (MF->getFunction().getAttributes().
+          hasAttrSomewhere(Attribute::InReg))
+        return CSR_Win_AArch64_SRet_AAPCS_SaveList;
     return CSR_Win_AArch64_AAPCS_SaveList;
+  }
   if (MF->getFunction().getCallingConv() == CallingConv::GHC)
     // GHC set of callee saved regs is empty as all those regs are
     // used for passing STG regs around