Index: llvm/trunk/lib/Target/AMDGPU/AMDGPU.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPU.td +++ llvm/trunk/lib/Target/AMDGPU/AMDGPU.td @@ -689,7 +689,7 @@ "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">, AssemblerPredicate<"!FeatureGCN3Encoding">; -def isGFX7 : +def isGFX7Only : Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">, AssemblerPredicate<"!FeatureGCN3Encoding,FeatureCIInsts">; @@ -707,18 +707,23 @@ Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">, AssemblerPredicate<"FeatureGFX8Insts">; +def isGFX8Only : Predicate<"Subtarget->getGeneration() ==" + "AMDGPUSubtarget::VOLCANIC_ISLANDS">, + AssemblerPredicate <"FeatureVolcanicIslands">; + def isGFX9Plus : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">, AssemblerPredicate<"FeatureGFX9Insts">; -def isVI : Predicate < - "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">, - AssemblerPredicate<"FeatureGCN3Encoding">; - -def isGFX9 : Predicate < +def isGFX9Only : Predicate < "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">, AssemblerPredicate<"FeatureGCN3Encoding,FeatureGFX9Insts">; +def isGFX8GFX9 : + Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||" + "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">, + AssemblerPredicate<"FeatureGFX8Insts,FeatureGCN3Encoding">; + def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">, AssemblerPredicate<"FeatureFlatAddressSpace">; Index: llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td +++ llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td @@ -830,7 +830,7 @@ // This is not described in AMD documentation, // but 'lds' versions of these opcodes are available // in at least GFX8+ chips. See Bug 37653. -let SubtargetPredicate = isVI in { +let SubtargetPredicate = isGFX8GFX9 in { defm BUFFER_LOAD_DWORDX2_LDS : MUBUF_Pseudo_Loads < "buffer_load_dwordx2", VReg_64, v2i32, null_frag, 0, 1 >; @@ -939,7 +939,7 @@ "buffer_atomic_dec_x2", VReg_64, i64, atomic_dec_global >; -let SubtargetPredicate = isVI in { +let SubtargetPredicate = isGFX8GFX9 in { def BUFFER_STORE_LDS_DWORD : MUBUF_Pseudo_Store_Lds <"buffer_store_lds_dword">; } @@ -1804,8 +1804,8 @@ class MUBUF_Real_ci op, MUBUF_Pseudo ps> : MUBUF_Real_si { - let AssemblerPredicate=isCIOnly; - let DecoderNamespace="GFX7"; + let AssemblerPredicate = isGFX7Only; + let DecoderNamespace = "GFX7"; } def BUFFER_WBINVL1_VOL_ci : MUBUF_Real_ci <0x70, BUFFER_WBINVL1_VOL>; @@ -1819,8 +1819,8 @@ MUBUF_Real, Enc64, SIMCInstr { - let AssemblerPredicate=isVI; - let DecoderNamespace="VI"; + let AssemblerPredicate = isGFX8GFX9; + let DecoderNamespace = "GFX8"; let Inst{11-0} = !if(ps.has_offset, offset, ?); let Inst{12} = ps.offen; @@ -1994,8 +1994,8 @@ MTBUF_Real, Enc64, SIMCInstr { - let AssemblerPredicate=isVI; - let DecoderNamespace="VI"; + let AssemblerPredicate = isGFX8GFX9; + let DecoderNamespace = "GFX8"; let Inst{11-0} = !if(ps.has_offset, offset, ?); let Inst{12} = ps.offen; Index: llvm/trunk/lib/Target/AMDGPU/DSInstructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/DSInstructions.td +++ llvm/trunk/lib/Target/AMDGPU/DSInstructions.td @@ -985,8 +985,8 @@ class DS_Real_vi op, DS_Pseudo ds> : DS_Real , SIMCInstr { - let AssemblerPredicates = [isVI]; - let DecoderNamespace="VI"; + let AssemblerPredicates = [isGFX8GFX9]; + let DecoderNamespace = "GFX8"; // encoding let Inst{7-0} = !if(ds.has_offset0, offset0, 0); Index: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -226,7 +226,7 @@ // Try decode 32-bit instruction if (Bytes.size() < 4) break; const uint32_t DW = eatBytes(Bytes); - Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address); + Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); if (Res) break; Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); @@ -237,7 +237,7 @@ if (Bytes.size() < 4) break; const uint64_t QW = ((uint64_t)eatBytes(Bytes) << 32) | DW; - Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address); + Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); if (Res) break; Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); Index: llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td +++ llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td @@ -493,7 +493,7 @@ VReg_64, i64, atomic_dec_flat>; // GFX7-only flat instructions. -let SubtargetPredicate = isGFX7 in { +let SubtargetPredicate = isGFX7Only in { defm FLAT_ATOMIC_FCMPSWAP : FLAT_Atomic_Pseudo <"flat_atomic_fcmpswap", VGPR_32, f32, null_frag, v2f32, VReg_64>; @@ -513,7 +513,7 @@ defm FLAT_ATOMIC_FMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmax_x2", VReg_64, f64>; -} // End SubtargetPredicate = isGFX7 +} // End SubtargetPredicate = isGFX7Only let SubtargetPredicate = HasFlatGlobalInsts in { defm GLOBAL_LOAD_UBYTE : FLAT_Global_Load_Pseudo <"global_load_ubyte", VGPR_32>; @@ -892,7 +892,7 @@ class FLAT_Real_ci op, FLAT_Pseudo ps> : FLAT_Real , SIMCInstr { - let AssemblerPredicate = isCIOnly; + let AssemblerPredicate = isGFX7Only; let DecoderNamespace="GFX7"; } @@ -960,8 +960,8 @@ class FLAT_Real_vi op, FLAT_Pseudo ps> : FLAT_Real , SIMCInstr { - let AssemblerPredicate = isVI; - let DecoderNamespace="VI"; + let AssemblerPredicate = isGFX8GFX9; + let DecoderNamespace = "GFX8"; } multiclass FLAT_Real_AllAddr_vi op> { Index: llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td +++ llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td @@ -267,10 +267,10 @@ let DisableDecoder = DisableSIDecoder; } - def _vi : MIMG_Atomic_Helper, + def _vi : MIMG_Atomic_Helper, SIMCInstr, MIMGe { - let AssemblerPredicates = [isVI]; + let AssemblerPredicates = [isGFX8GFX9]; let DisableDecoder = DisableVIDecoder; let MIMGEncoding = MIMGEncGfx8; } Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td +++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td @@ -5,20 +5,12 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -def isCI : Predicate<"Subtarget->getGeneration() " - ">= AMDGPUSubtarget::SEA_ISLANDS">; -def isCIOnly : Predicate<"Subtarget->getGeneration() ==" - "AMDGPUSubtarget::SEA_ISLANDS">, - AssemblerPredicate <"FeatureSeaIslands">; -def isVIOnly : Predicate<"Subtarget->getGeneration() ==" - "AMDGPUSubtarget::VOLCANIC_ISLANDS">, - AssemblerPredicate <"FeatureVolcanicIslands">; def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">; class GCNPredicateControl : PredicateControl { Predicate SIAssemblerPredicate = isGFX6GFX7; - Predicate VIAssemblerPredicate = isVI; + Predicate VIAssemblerPredicate = isGFX8GFX9; } // Execpt for the NONE field, this must be kept in sync with the @@ -1157,8 +1149,8 @@ def _vi : EXP_Helper, SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.VI>, EXPe_vi { - let AssemblerPredicates = [isVI]; - let DecoderNamespace = "VI"; + let AssemblerPredicates = [isGFX8GFX9]; + let DecoderNamespace = "GFX8"; let DisableDecoder = DisableVIDecoder; } } @@ -2016,7 +2008,7 @@ VINTRPe_vi , SIMCInstr { let AssemblerPredicate = VIAssemblerPredicate; - let DecoderNamespace = "VI"; + let DecoderNamespace = "GFX8"; let DisableDecoder = DisableVIDecoder; } Index: llvm/trunk/lib/Target/AMDGPU/SMInstructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SMInstructions.td +++ llvm/trunk/lib/Target/AMDGPU/SMInstructions.td @@ -375,7 +375,7 @@ } // let SubtargetPredicate = HasScalarAtomics -let SubtargetPredicate = isGFX9 in { +let SubtargetPredicate = isGFX9Only in { defm S_DCACHE_DISCARD : SM_Pseudo_Discards <"s_dcache_discard">; defm S_DCACHE_DISCARD_X2 : SM_Pseudo_Discards <"s_dcache_discard_x2">; } @@ -447,8 +447,8 @@ , Enc64 { bit glc; - let AssemblerPredicates = [isVI]; - let DecoderNamespace = "VI"; + let AssemblerPredicates = [isGFX8GFX9]; + let DecoderNamespace = "GFX8"; let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?); let Inst{12-6} = !if(ps.has_sdst, sdst{6-0}, ?); @@ -636,7 +636,7 @@ SM_Real, Enc64 { - let AssemblerPredicates = [isGFX7]; + let AssemblerPredicates = [isGFX7Only]; let DecoderNamespace = "GFX7"; let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, GLC:$glc); @@ -673,7 +673,7 @@ , SIMCInstr , Enc32 { - let AssemblerPredicates = [isGFX7]; + let AssemblerPredicates = [isGFX7Only]; let DecoderNamespace = "GFX7"; let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?); @@ -725,7 +725,7 @@ def : GCNPat < (smrd_load (SMRDImm32 i64:$sbase, i32:$offset)), (vt (!cast(Instr#"_IMM_ci") $sbase, $offset, 0))> { - let OtherPredicates = [isGFX7]; + let OtherPredicates = [isGFX7Only]; } // 3. SGPR offset @@ -752,7 +752,7 @@ def : GCNPat < (vt (SIsbuffer_load v4i32:$sbase, (SMRDBufferImm32 i32:$offset), i1:$glc)), (!cast(Instr#"_IMM_ci") $sbase, $offset, (as_i1imm $glc))> { - let OtherPredicates = [isCIOnly]; + let OtherPredicates = [isGFX7Only]; } // 3. Offset loaded in an 32bit SGPR @@ -793,11 +793,11 @@ >; } -let OtherPredicates = [isVI] in { +let OtherPredicates = [isGFX8Plus] in { def : GCNPat < (i64 (readcyclecounter)), (S_MEMREALTIME) >; -} // let OtherPredicates = [isVI] +} // let OtherPredicates = [isGFX8Plus] Index: llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td +++ llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td @@ -526,7 +526,7 @@ def S_ABSDIFF_I32 : SOP2_32 <"s_absdiff_i32">; } // End Defs = [SCC] -let SubtargetPredicate = isVI in { +let SubtargetPredicate = isGFX8GFX9 in { def S_RFE_RESTORE_B64 : SOP2_Pseudo < "s_rfe_restore_b64", (outs), (ins SSrc_b64:$src0, SSrc_b32:$src1), @@ -1261,8 +1261,8 @@ class Select_vi : SIMCInstr { - list AssemblerPredicates = [isVI]; - string DecoderNamespace = "VI"; + list AssemblerPredicates = [isGFX8GFX9]; + string DecoderNamespace = "GFX8"; } class SOP1_Real_vi op, SOP1_Pseudo ps> : Index: llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td +++ llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td @@ -405,9 +405,9 @@ defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16>; } // End SubtargetPredicate = isGFX9Plus -let SubtargetPredicate = isGFX9 in { +let SubtargetPredicate = isGFX9Only in { defm V_SCREEN_PARTITION_4SE_B32 : VOP1Inst <"v_screen_partition_4se_b32", VOP_I32_I32>; -} // End SubtargetPredicate = isGFX9 +} // End SubtargetPredicate = isGFX9Only //===----------------------------------------------------------------------===// // Target @@ -493,7 +493,7 @@ //===----------------------------------------------------------------------===// multiclass VOP1_Real_ci op> { - let AssemblerPredicates = [isCIOnly], DecoderNamespace = "GFX7" in { + let AssemblerPredicates = [isGFX7Only], DecoderNamespace = "GFX7" in { def _e32_ci : VOP1_Real(NAME#"_e32"), SIEncodingFamily.SI>, VOP1e(NAME#"_e32").Pfl>; @@ -524,7 +524,7 @@ } multiclass VOP1Only_Real_vi op> { - let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in { + let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in { def _vi : VOP1_Real(NAME), SIEncodingFamily.VI>, VOP1e(NAME).Pfl>; @@ -532,7 +532,7 @@ } multiclass VOP1_Real_e32e64_vi op> { - let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in { + let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in { def _e32_vi : VOP1_Real(NAME#"_e32"), SIEncodingFamily.VI>, VOP1e(NAME#"_e32").Pfl>; @@ -649,7 +649,7 @@ PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT.ret:$vdst, getVOPSrc0ForVT.ret:$src0)> { let VOP1 = 1; - let SubtargetPredicate = isVI; + let SubtargetPredicate = isGFX8GFX9; } // This is a pseudo variant of the v_movreld_b32 instruction in which the @@ -672,7 +672,7 @@ def V_MOVRELD_B32_V8 : V_MOVRELD_B32_pseudo; def V_MOVRELD_B32_V16 : V_MOVRELD_B32_pseudo; -let OtherPredicates = [isVI] in { +let OtherPredicates = [isGFX8GFX9] in { def : GCNPat < (i32 (int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$row_mask, imm:$bank_mask, @@ -690,7 +690,7 @@ (as_i1imm $bound_ctrl)) >; -} // End OtherPredicates = [isVI] +} // End OtherPredicates = [isGFX8GFX9] let OtherPredicates = [isGFX8Plus] in { def : GCNPat< @@ -722,7 +722,7 @@ //===----------------------------------------------------------------------===// multiclass VOP1_Real_gfx9 op> { - let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in { + let AssemblerPredicates = [isGFX9Only], DecoderNamespace = "GFX9" in { defm NAME : VOP1_Real_e32e64_vi ; } Index: llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td +++ llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td @@ -815,7 +815,7 @@ let Inst{31} = 0x0; //encoding } -let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in { +let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in { multiclass VOP2_Real_MADK_vi op> { def _vi : VOP2_Real(NAME), SIEncodingFamily.VI>, @@ -849,7 +849,7 @@ VOP2_Real_e32_vi, VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>; -} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI" +} // End AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" multiclass VOP2_SDWA_Real op> { def _sdwa_vi : @@ -863,7 +863,7 @@ VOP2_SDWA9Ae (NAME#"_sdwa").Pfl>; } -let AssemblerPredicates = [isVIOnly] in { +let AssemblerPredicates = [isGFX8Only] in { multiclass VOP2be_Real_e32e64_vi_only op, string OpName, string AsmName> { def _e32_vi : @@ -871,14 +871,14 @@ VOP2e(OpName#"_e32").Pfl> { VOP2_Pseudo ps = !cast(OpName#"_e32"); let AsmString = AsmName # ps.AsmOperands; - let DecoderNamespace = "VI"; + let DecoderNamespace = "GFX8"; } def _e64_vi : VOP3_Real(OpName#"_e64"), SIEncodingFamily.VI>, VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast(OpName#"_e64").Pfl> { VOP3_Pseudo ps = !cast(OpName#"_e64"); let AsmString = AsmName # ps.AsmOperands; - let DecoderNamespace = "VI"; + let DecoderNamespace = "GFX8"; } def _sdwa_vi : VOP_SDWA_Real (OpName#"_sdwa")>, @@ -896,7 +896,7 @@ } } -let AssemblerPredicates = [isGFX9] in { +let AssemblerPredicates = [isGFX9Only] in { multiclass VOP2be_Real_e32e64_gfx9 op, string OpName, string AsmName> { def _e32_gfx9 : @@ -952,7 +952,7 @@ } } -} // AssemblerPredicates = [isGFX9] +} // AssemblerPredicates = [isGFX9Only] multiclass VOP2_Real_e32e64_vi op> : Base_VOP2_Real_e32e64_vi, VOP2_SDWA_Real, VOP2_SDWA9_Real { @@ -1041,7 +1041,7 @@ defm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>; defm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>; -let SubtargetPredicate = isVI in { +let SubtargetPredicate = isGFX8GFX9 in { // Aliases to simplify matching of floating-point instructions that // are VOP2 on SI and VOP3 on VI. @@ -1061,7 +1061,7 @@ def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>; def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>; -} // End SubtargetPredicate = isVI +} // End SubtargetPredicate = isGFX8GFX9 let SubtargetPredicate = HasDLInsts in { Index: llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td +++ llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td @@ -400,7 +400,7 @@ } // End SubtargetPredicate = isGFX8Plus } // End SchedRW = [Write64Bit] -let Predicates = [isVI] in { +let Predicates = [isGFX8Plus] in { def : GCNPat < (getDivergentFrag.ret i64:$x, i32:$y), (V_LSHLREV_B64 $y, $x) @@ -440,7 +440,7 @@ def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile, AMDGPUdiv_fixup> { - let Predicates = [Has16BitInsts, isVIOnly]; + let Predicates = [Has16BitInsts, isGFX8Only]; let FPDPRounding = 1; } def V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9", @@ -451,7 +451,7 @@ } def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile, fma> { - let Predicates = [Has16BitInsts, isVIOnly]; + let Predicates = [Has16BitInsts, isGFX8Only]; let FPDPRounding = 1; } def V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile, fma> { @@ -480,11 +480,11 @@ } // End FPDPRounding = 1 } // End renamedInGFX9 = 1 -let SubtargetPredicate = isGFX9 in { +let SubtargetPredicate = isGFX9Only in { def V_MAD_F16_gfx9 : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile> { let FPDPRounding = 1; } -} // End SubtargetPredicate = isGFX9 +} // End SubtargetPredicate = isGFX9Only let SubtargetPredicate = isGFX9Plus in { def V_MAD_U16_gfx9 : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile>; @@ -513,11 +513,11 @@ } // End SubtargetPredicate = Has16BitInsts, isCommutable = 1 -let SubtargetPredicate = isVI in { +let SubtargetPredicate = isGFX8GFX9 in { def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>; def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>; def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>; -} // End SubtargetPredicate = isVI +} // End SubtargetPredicate = isGFX8GFX9 let Predicates = [Has16BitInsts] in { @@ -741,7 +741,7 @@ multiclass VOP3_Real_ci op> { def _ci : VOP3_Real(NAME), SIEncodingFamily.SI>, VOP3e_si (NAME).Pfl> { - let AssemblerPredicates = [isCIOnly]; + let AssemblerPredicates = [isGFX7Only]; let DecoderNamespace = "GFX7"; } } @@ -749,7 +749,7 @@ multiclass VOP3be_Real_ci op> { def _ci : VOP3_Real(NAME), SIEncodingFamily.SI>, VOP3be_si (NAME).Pfl> { - let AssemblerPredicates = [isCIOnly]; + let AssemblerPredicates = [isGFX7Only]; let DecoderNamespace = "GFX7"; } } @@ -763,7 +763,7 @@ // GFX8, GFX9 (VI). //===----------------------------------------------------------------------===// -let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in { +let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in { multiclass VOP3_Real_vi op> { def _vi : VOP3_Real(NAME), SIEncodingFamily.VI>, @@ -785,9 +785,9 @@ VOP3Interp_vi (NAME).Pfl>; } -} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI" +} // End AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" -let AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI" in { +let AssemblerPredicates = [isGFX8Only], DecoderNamespace = "GFX8" in { multiclass VOP3_F16_Real_vi op> { def _vi : VOP3_Real(NAME), SIEncodingFamily.VI>, @@ -799,9 +799,9 @@ VOP3Interp_vi (NAME).Pfl>; } -} // End AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI" +} // End AssemblerPredicates = [isGFX8Only], DecoderNamespace = "GFX8" -let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in { +let AssemblerPredicates = [isGFX9Only], DecoderNamespace = "GFX9" in { multiclass VOP3_F16_Real_gfx9 op, string OpName, string AsmName> { def _gfx9 : VOP3_Real(OpName), SIEncodingFamily.GFX9>, @@ -835,7 +835,7 @@ } } -} // End AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" +} // End AssemblerPredicates = [isGFX9Only], DecoderNamespace = "GFX9" defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>; defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>; Index: llvm/trunk/lib/Target/AMDGPU/VOP3PInstructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/VOP3PInstructions.td +++ llvm/trunk/lib/Target/AMDGPU/VOP3PInstructions.td @@ -318,7 +318,7 @@ def _vi : VOP3P_Real(NAME), SIEncodingFamily.VI>, VOP3Pe (NAME).Pfl> { let AssemblerPredicates = [HasVOP3PInsts]; - let DecoderNamespace = "VI"; + let DecoderNamespace = "GFX8"; } } Index: llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td +++ llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td @@ -940,7 +940,7 @@ //===----------------------------------------------------------------------===// multiclass VOPC_Real_vi op> { - let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in { + let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in { def _e32_vi : VOPC_Real(NAME#"_e32"), SIEncodingFamily.VI>, VOPCe; @@ -965,7 +965,7 @@ def : VOPCInstAlias (NAME#"_e64"), !cast(NAME#"_e32_vi")> { - let AssemblerPredicate = isVI; + let AssemblerPredicate = isGFX8GFX9; } }