Index: llvm/include/llvm/Support/TargetOpcodes.def
===================================================================
--- llvm/include/llvm/Support/TargetOpcodes.def
+++ llvm/include/llvm/Support/TargetOpcodes.def
@@ -442,6 +442,9 @@
 /// Generic FP exponentiation.
 HANDLE_TARGET_OPCODE(G_FPOW)
 
+/// Generic FP exponentiation with integer power.
+HANDLE_TARGET_OPCODE(G_FPOWI)
+
 /// Generic base-e exponential of a value.
 HANDLE_TARGET_OPCODE(G_FEXP)
 
Index: llvm/include/llvm/Target/GenericOpcodes.td
===================================================================
--- llvm/include/llvm/Target/GenericOpcodes.td
+++ llvm/include/llvm/Target/GenericOpcodes.td
@@ -519,6 +519,13 @@
   let hasSideEffects = 0;
 }
 
+// Floating point exponentiation with integer power.
+def G_FPOWI : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src1, type0:$src2);
+  let hasSideEffects = 0;
+}
+
 // Floating point base-e exponential of a value.
 def G_FEXP : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
Index: llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -821,6 +821,8 @@
       return TargetOpcode::G_FLOG10;
     case Intrinsic::pow:
       return TargetOpcode::G_FPOW;
+    case Intrinsic::powi:
+      return TargetOpcode::G_FPOWI;
     case Intrinsic::round:
       return TargetOpcode::G_INTRINSIC_ROUND;
     case Intrinsic::sin:
Index: llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -2371,3 +2371,14 @@
   call void @llvm.stackrestore(i8* %sp)
   ret void
 }
+
+declare float @llvm.powi.f32(float, i32)
+define float @test_powi_intrin(float %l, i32 %r) {
+    ; CHECK-LABEL: name: test_powi_intrin
+    ; CHECK: [[REG1:%[0-9]+]]:_(s32) = COPY $s0
+    ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[REG3:%[0-9]+]]:_(s32) = G_FPOWI [[REG1]], [[REG2]]
+    ; CHECK-NEXT: $s0 = COPY [[REG3]](s32)
+  %res = call float @llvm.powi.f32(float %l, i32 %r)
+  ret float %res
+}
Index: llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -255,6 +255,9 @@
 # DEBUG-NEXT: G_FPOW (opcode {{[0-9]+}}): 1 type index
 # DEBUG:      .. the first uncovered type index: 1, OK
 #
+# DEBUG-NEXT: G_FPOWI (opcode {{[0-9]+}}): 1 type index
+# DEBUG:      .. type index coverage check SKIPPED: no rules defined
+#
 # DEBUG-NEXT: G_FEXP (opcode {{[0-9]+}}): 1 type index
 # DEBUG:      .. the first uncovered type index: 1, OK
 #