Index: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp =================================================================== --- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -244,6 +244,9 @@ case TargetOpcode::G_FEXP: assert((Size == 32 || Size == 64) && "Unsupported size"); return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32; + case TargetOpcode::G_FEXP2: + assert((Size == 32 || Size == 64) && "Unsupported size"); + return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32; case TargetOpcode::G_FREM: return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32; case TargetOpcode::G_FPOW: @@ -368,7 +371,8 @@ case TargetOpcode::G_FLOG10: case TargetOpcode::G_FLOG: case TargetOpcode::G_FLOG2: - case TargetOpcode::G_FEXP: { + case TargetOpcode::G_FEXP: + case TargetOpcode::G_FEXP2: { if (Size > 64) { LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n"); return UnableToLegalize; @@ -1345,6 +1349,7 @@ case TargetOpcode::G_FLOG2: case TargetOpcode::G_FSQRT: case TargetOpcode::G_FEXP: + case TargetOpcode::G_FEXP2: assert(TypeIdx == 0); Observer.changingInstr(MI); Index: llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp +++ llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp @@ -146,7 +146,7 @@ .legalFor({s16, s32, s64, v2s32, v4s32, v2s64, v2s16, v4s16, v8s16}); getActionDefinitionsBuilder( - {G_FCOS, G_FSIN, G_FLOG10, G_FLOG, G_FLOG2, G_FEXP}) + {G_FCOS, G_FSIN, G_FLOG10, G_FLOG, G_FLOG2, G_FEXP, G_FEXP2}) // We need a call for these, so we always need to scalarize. .scalarize(0) // Regardless of FP16 support, widen 16-bit elements to 32-bits. Index: llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir @@ -0,0 +1,252 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -verify-machineinstrs -mtriple aarch64--- \ +# RUN: -run-pass=legalizer -mattr=+fullfp16 -global-isel %s -o - \ +# RUN: | FileCheck %s +... +--- +name: test_v4f16.exp2 +alignment: 2 +tracksRegLiveness: true +body: | + bb.0: + liveins: $d0 + ; CHECK-LABEL: name: test_v4f16.exp2 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 + ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) + ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16) + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[FPEXT]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY1]](s32) + ; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16) + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[FPEXT1]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY2]](s32) + ; CHECK: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16) + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[FPEXT2]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY3]](s32) + ; CHECK: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16) + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[FPEXT3]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY4]](s32) + ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16) + ; CHECK: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>) + ; CHECK: RET_ReallyLR implicit $d0 + %0:_(<4 x s16>) = COPY $d0 + %1:_(<4 x s16>) = G_FEXP2 %0 + $d0 = COPY %1(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_v8f16.exp2 +alignment: 2 +tracksRegLiveness: true +body: | + bb.0: + liveins: $q0 + ; CHECK-LABEL: name: test_v8f16.exp2 + ; CHECK: liveins: $q0 + ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 + ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<8 x s16>) + ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16) + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[FPEXT]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY1]](s32) + ; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16) + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[FPEXT1]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY2]](s32) + ; CHECK: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16) + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[FPEXT2]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY3]](s32) + ; CHECK: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16) + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[FPEXT3]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY4]](s32) + ; CHECK: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[UV4]](s16) + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[FPEXT4]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY5]](s32) + ; CHECK: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[UV5]](s16) + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[FPEXT5]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY6]](s32) + ; CHECK: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[UV6]](s16) + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[FPEXT6]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY7]](s32) + ; CHECK: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[UV7]](s16) + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[FPEXT7]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY8]](s32) + ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16), [[FPTRUNC4]](s16), [[FPTRUNC5]](s16), [[FPTRUNC6]](s16), [[FPTRUNC7]](s16) + ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<8 x s16>) + ; CHECK: RET_ReallyLR implicit $q0 + %0:_(<8 x s16>) = COPY $q0 + %1:_(<8 x s16>) = G_FEXP2 %0 + $q0 = COPY %1(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_v2f32.exp2 +alignment: 2 +tracksRegLiveness: true +body: | + bb.0: + liveins: $d0 + ; CHECK-LABEL: name: test_v2f32.exp2 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 + ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[UV]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[UV1]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32) + ; CHECK: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>) + ; CHECK: RET_ReallyLR implicit $d0 + %0:_(<2 x s32>) = COPY $d0 + %1:_(<2 x s32>) = G_FEXP2 %0 + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_v4f32.exp2 +alignment: 2 +tracksRegLiveness: true +body: | + bb.0: + liveins: $q0 + ; CHECK-LABEL: name: test_v4f32.exp2 + ; CHECK: liveins: $q0 + ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 + ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>) + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[UV]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[UV1]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[UV2]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[UV3]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32) + ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>) + ; CHECK: RET_ReallyLR implicit $q0 + %0:_(<4 x s32>) = COPY $q0 + %1:_(<4 x s32>) = G_FEXP2 %0 + $q0 = COPY %1(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_v2f64.exp2 +alignment: 2 +tracksRegLiveness: true +body: | + bb.0: + liveins: $q0 + ; CHECK-LABEL: name: test_v2f64.exp2 + ; CHECK: liveins: $q0 + ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 + ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $d0 = COPY [[UV]](s64) + ; CHECK: BL &exp2, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit-def $d0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $d0 = COPY [[UV1]](s64) + ; CHECK: BL &exp2, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit-def $d0 + ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY1]](s64), [[COPY2]](s64) + ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x s64>) + ; CHECK: RET_ReallyLR implicit $q0 + %0:_(<2 x s64>) = COPY $q0 + %1:_(<2 x s64>) = G_FEXP2 %0 + $q0 = COPY %1(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_exp2_half +alignment: 2 +tracksRegLiveness: true +body: | + bb.0: + liveins: $h0 + ; CHECK-LABEL: name: test_exp2_half + ; CHECK: liveins: $h0 + ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $h0 + ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[COPY]](s16) + ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK: $s0 = COPY [[FPEXT]](s32) + ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY1]](s32) + ; CHECK: $h0 = COPY [[FPTRUNC]](s16) + ; CHECK: RET_ReallyLR implicit $h0 + %0:_(s16) = COPY $h0 + %1:_(s16) = G_FEXP2 %0 + $h0 = COPY %1(s16) + RET_ReallyLR implicit $h0 Index: llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir =================================================================== --- llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir +++ llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir @@ -259,7 +259,7 @@ # DEBUG: .. the first uncovered type index: 1, OK # # DEBUG-NEXT: G_FEXP2 (opcode {{[0-9]+}}): 1 type index -# DEBUG: .. type index coverage check SKIPPED: no rules defined +# DEBUG: .. the first uncovered type index: 1, OK # # DEBUG-NEXT: G_FLOG (opcode {{[0-9]+}}): 1 type index # DEBUG: .. the first uncovered type index: 1, OK Index: llvm/test/CodeGen/AArch64/f16-instructions.ll =================================================================== --- llvm/test/CodeGen/AArch64/f16-instructions.ll +++ llvm/test/CodeGen/AArch64/f16-instructions.ll @@ -919,6 +919,15 @@ ; CHECK-COMMON-NEXT: fcvt h0, s0 ; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16 ; CHECK-COMMON-NEXT: ret + +; GISEL-LABEL: test_exp2: +; GISEL-NEXT: stp x29, x30, [sp, #-16]! +; GISEL-NEXT: mov x29, sp +; GISEL-NEXT: fcvt s0, h0 +; GISEL-NEXT: bl {{_?}}exp2f +; GISEL-NEXT: fcvt h0, s0 +; GISEL-NEXT: ldp x29, x30, [sp], #16 +; GISEL-NEXT: ret define half @test_exp2(half %a) #0 { %r = call half @llvm.exp2.f16(half %a) ret half %r