Index: lib/Target/Mips/MipsInstrFPU.td =================================================================== --- lib/Target/Mips/MipsInstrFPU.td +++ lib/Target/Mips/MipsInstrFPU.td @@ -528,6 +528,10 @@ BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6; def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, IIBranch, MIPS_BRANCH_T, 0>, BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6; +def BC2F : MMRel, BC1F_FT<"bc2f", brtarget, IIBranch, MIPS_BRANCH_F>, + BC2F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6; +def BC2T : MMRel, BC1F_FT<"bc2t", brtarget, IIBranch, MIPS_BRANCH_T>, + BC2F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6; //===----------------------------------------------------------------------===// // Floating Point Flag Conditions @@ -599,6 +603,10 @@ ISA_MIPS1_NOT_32R6_64R6; def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>, ISA_MIPS2_NOT_32R6_64R6; +def : MipsInstAlias<"bc2f $offset", (BC2F FCC0, brtarget:$offset)>, + ISA_MIPS1_NOT_32R6_64R6; +def : MipsInstAlias<"bc2t $offset", (BC2T FCC0, brtarget:$offset)>, + ISA_MIPS1_NOT_32R6_64R6; //===----------------------------------------------------------------------===// // Floating Point Patterns Index: lib/Target/Mips/MipsInstrFormats.td =================================================================== --- lib/Target/Mips/MipsInstrFormats.td +++ lib/Target/Mips/MipsInstrFormats.td @@ -778,6 +778,20 @@ let Inst{15-0} = offset; } +class BC2F_FM : StdArch { + bits<3> fcc; + bits<16> offset; + + bits<32> Inst; + + let Inst{31-26} = 0x12; + let Inst{25-21} = 0x8; + let Inst{20-18} = fcc; + let Inst{17} = nd; + let Inst{16} = tf; + let Inst{15-0} = offset; +} + class CEQS_FM fmt> : StdArch { bits<5> fs; bits<5> ft; Index: test/MC/Disassembler/Mips/mips32.txt =================================================================== --- test/MC/Disassembler/Mips/mips32.txt +++ test/MC/Disassembler/Mips/mips32.txt @@ -45,6 +45,18 @@ # CHECK: bc1t $fcc7, 1332 0x45 0x1d 0x01 0x4d +# CHECK: bc2f 1332 +0x49 0x00 0x01 0x4d + +# CHECK: bc2f $fcc7, 1332 +0x49 0x1c 0x01 0x4d + +# CHECK: bc2t 1332 +0x49 0x01 0x01 0x4d + +# CHECK: bc2t $fcc7, 1332 +0x49 0x1d 0x01 0x4d + # CHECK: beq $9, $6, 1332 0x11 0x26 0x01 0x4d Index: test/MC/Mips/mips1/valid.s =================================================================== --- test/MC/Mips/mips1/valid.s +++ test/MC/Mips/mips1/valid.s @@ -22,6 +22,10 @@ bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc2f $fcc0, 4 # CHECK: bc2f 4 # encoding: [0x49,0x00,0x00,0x01] + bc2f 4 # CHECK: bc2f 4 # encoding: [0x49,0x00,0x00,0x01] + bc2t $fcc0, 4 # CHECK: bc2t 4 # encoding: [0x49,0x01,0x00,0x01] + bc2t 4 # CHECK: bc2t 4 # encoding: [0x49,0x01,0x00,0x01] bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] Index: test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s =================================================================== --- test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s +++ test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s @@ -5,8 +5,6 @@ # RUN: FileCheck %s < %t1 .set noat - bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction Index: test/MC/Mips/mips32r6/invalid-mips1.s =================================================================== --- test/MC/Mips/mips32r6/invalid-mips1.s +++ test/MC/Mips/mips32r6/invalid-mips1.s @@ -8,6 +8,8 @@ add $9,$14,15176 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled add $24,-7193 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.sf.d $f30,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled Index: test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s =================================================================== --- test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s +++ test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s @@ -6,10 +6,6 @@ # RUN: FileCheck %s < %t1 .set noat - bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction Index: test/MC/Mips/mips32r6/invalid-mips32.s =================================================================== --- test/MC/Mips/mips32r6/invalid-mips32.s +++ test/MC/Mips/mips32r6/invalid-mips32.s @@ -7,6 +7,10 @@ .set noat bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled Index: test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s =================================================================== --- test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s +++ test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s @@ -5,8 +5,6 @@ # RUN: FileCheck %s < %t1 .set noat - bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction Index: test/MC/Mips/mips64r6/invalid-mips1.s =================================================================== --- test/MC/Mips/mips64r6/invalid-mips1.s +++ test/MC/Mips/mips64r6/invalid-mips1.s @@ -8,6 +8,8 @@ add $9,$14,15176 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled add $24,-7193 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled Index: test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s =================================================================== --- test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s +++ test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s @@ -6,11 +6,7 @@ # RUN: FileCheck %s < %t1 .set noat - bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction Index: test/MC/Mips/mips64r6/invalid-mips32.s =================================================================== --- /dev/null +++ test/MC/Mips/mips64r6/invalid-mips32.s @@ -0,0 +1,13 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + + .set noat + bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled +