Index: lib/Target/Mips/MicroMipsInstrFPU.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrFPU.td
+++ lib/Target/Mips/MicroMipsInstrFPU.td
@@ -42,10 +42,24 @@
   bits<3> fcc = 0;
 }
 
-def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>,
-              BC1F_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6;
-def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>,
-              BC1F_FM_MM<0x1d>, ISA_MIPS1_NOT_32R6_64R6;
+def BC1F_MM : MMRel, BCXFT_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>,
+              BCXFT_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6;
+def BC1T_MM : MMRel, BCXFT_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>,
+              BCXFT_FM_MM<0x1d>, ISA_MIPS1_NOT_32R6_64R6;
+def BC2F_MM : MMRel, BCXFT_FT<"bc2f", brtarget_mm, II_BC2F, MIPS_BRANCH_F>,
+              BCXFT_FM_MM<0x14>, ISA_MIPS1_NOT_32R6_64R6 {
+  // Unselectable by default as Coprocessor 2 is implementation dependant.
+  list<dag> Pattern = [];
+  let AdditionalPredicates = [NotCnMips];
+}
+
+def BC2T_MM : MMRel, BCXFT_FT<"bc2t", brtarget_mm, II_BC2T, MIPS_BRANCH_T>,
+              BCXFT_FM_MM<0x15>, ISA_MIPS1_NOT_32R6_64R6 {
+  // Unselectable by default as Coprocessor 2 is implementation dependant.
+  list<dag> Pattern = [];
+  let AdditionalPredicates = [NotCnMips];
+}
+
 def CVT_W_S_MM   : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
                    ROUND_W_FM_MM<0, 0x24>;
 def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
@@ -265,7 +279,9 @@
   defm D64_MM : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT,
                 ISA_MIPS1_NOT_32R6_64R6, FGR_64;
 
-  defm : BC1_ALIASES<BC1T_MM, "bc1t", BC1F_MM, "bc1f">,
+  defm : BCX_ALIASES<BC1T_MM, "bc1t", BC1F_MM, "bc1f">,
+         ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT;
+  defm : BCX_ALIASES<BC2T_MM, "bc2t", BC2F_MM, "bc2f">,
          ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT;
 }
 
Index: lib/Target/Mips/MicroMipsInstrFormats.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrFormats.td
+++ lib/Target/Mips/MicroMipsInstrFormats.td
@@ -785,14 +785,15 @@
   let cond = c;
 }
 
-class BC1F_FM_MM<bits<5> tf> : MMArch {
+class BCXFT_FM_MM<bits<5> tf> : MMArch {
+  bits<3> fcc;
   bits<16> offset;
 
   bits<32> Inst;
 
   let Inst{31-26} = 0x10;
   let Inst{25-21} = tf;
-  let Inst{20-18} = 0x0; // cc
+  let Inst{20-18} = fcc;
   let Inst{17-16} = 0x0;
   let Inst{15-0}  = offset;
 }
Index: lib/Target/Mips/MipsInstrFPU.td
===================================================================
--- lib/Target/Mips/MipsInstrFPU.td
+++ lib/Target/Mips/MipsInstrFPU.td
@@ -209,7 +209,7 @@
   let AddedComplexity = 20;
 }
 
-class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
+class BCXFT_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
               SDPatternOperator Op = null_frag, bit DelaySlot = 1> :
   InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
          !strconcat(opstr, "\t$fcc, $offset"),
@@ -603,15 +603,28 @@
 def MIPS_BRANCH_F  : PatLeaf<(i32 0)>;
 def MIPS_BRANCH_T  : PatLeaf<(i32 1)>;
 
-def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
+def BC1F : MMRel, BCXFT_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
            BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
-def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, II_BC1FL, MIPS_BRANCH_F, 0>,
+def BC1FL : MMRel, BCXFT_FT<"bc1fl", brtarget, II_BC1FL, MIPS_BRANCH_F, 0>,
             BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
-def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
+def BC1T : MMRel, BCXFT_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
            BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
-def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, II_BC1TL, MIPS_BRANCH_T, 0>,
+def BC1TL : MMRel, BCXFT_FT<"bc1tl", brtarget, II_BC1TL, MIPS_BRANCH_T, 0>,
             BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
 
+def BC2F : MMRel, BCXFT_FT<"bc2f", brtarget, II_BC2F, MIPS_BRANCH_F>,
+           BC2F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6 {
+  // Unselectable by default as Coprocessor 2 is implementation dependant.
+  list<dag> Pattern = [];
+  let AdditionalPredicates = [NotCnMips];
+}
+def BC2T : MMRel, BCXFT_FT<"bc2t", brtarget, II_BC2T, MIPS_BRANCH_T>,
+           BC2F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6 {
+  // Unselectable by default as Coprocessor 2 is implementation dependant.
+  list<dag> Pattern = [];
+  let AdditionalPredicates = [NotCnMips];
+}
+
 /// Floating Point Compare
 let AdditionalPredicates = [NotInMicroMips] in {
   def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,
@@ -755,7 +768,7 @@
                                                          RC:$fs, RC:$ft), 1>;
 }
 
-multiclass BC1_ALIASES<Instruction BCTrue, string BCTrueString,
+multiclass BCX_ALIASES<Instruction BCTrue, string BCTrueString,
                        Instruction BCFalse, string BCFalseString> {
   def : MipsInstAlias<!strconcat(BCTrueString, " $offset"),
                                 (BCTrue FCC0, brtarget:$offset), 1>;
@@ -772,9 +785,11 @@
   defm D64 : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT,
              ISA_MIPS1_NOT_32R6_64R6, FGR_64;
 
-  defm : BC1_ALIASES<BC1T, "bc1t", BC1F, "bc1f">, ISA_MIPS1_NOT_32R6_64R6,
+  defm : BCX_ALIASES<BC1T, "bc1t", BC1F, "bc1f">, ISA_MIPS1_NOT_32R6_64R6,
+         HARDFLOAT;
+  defm : BCX_ALIASES<BC1TL, "bc1tl", BC1FL, "bc1fl">, ISA_MIPS2_NOT_32R6_64R6,
          HARDFLOAT;
-  defm : BC1_ALIASES<BC1TL, "bc1tl", BC1FL, "bc1fl">, ISA_MIPS2_NOT_32R6_64R6,
+  defm : BCX_ALIASES<BC2T, "bc2t", BC2F, "bc2f">, ISA_MIPS1_NOT_32R6_64R6,
          HARDFLOAT;
 }
 //===----------------------------------------------------------------------===//
Index: lib/Target/Mips/MipsInstrFormats.td
===================================================================
--- lib/Target/Mips/MipsInstrFormats.td
+++ lib/Target/Mips/MipsInstrFormats.td
@@ -829,6 +829,20 @@
   let Inst{15-0} = offset;
 }
 
+class BC2F_FM<bit nd, bit tf> : StdArch {
+  bits<3>  fcc;
+  bits<16> offset;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0x12;
+  let Inst{25-21} = 0x8;
+  let Inst{20-18} = fcc;
+  let Inst{17} = nd;
+  let Inst{16} = tf;
+  let Inst{15-0} = offset;
+}
+
 class CEQS_FM<bits<5> fmt> : StdArch {
   bits<5> fs;
   bits<5> ft;
Index: lib/Target/Mips/MipsSchedule.td
===================================================================
--- lib/Target/Mips/MipsSchedule.td
+++ lib/Target/Mips/MipsSchedule.td
@@ -45,6 +45,8 @@
 def II_BC1TL            : InstrItinClass;
 def II_BC1CCZ           : InstrItinClass;
 def II_BC2CCZ           : InstrItinClass;
+def II_BC2T             : InstrItinClass;
+def II_BC2F             : InstrItinClass;
 def II_BCC              : InstrItinClass; // beq and bne
 def II_BCCZ             : InstrItinClass; // b[gl][et]z
 def II_BCCC             : InstrItinClass; // b<cc>c
@@ -478,6 +480,8 @@
   InstrItinData<II_BC1T            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_BC1TL           , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_BC1CCZ          , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_BC2F            , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_BC2T            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_BC2CCZ          , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_BCC             , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_BCCC            , [InstrStage<1,  [ALU]>]>,
Index: lib/Target/Mips/MipsScheduleGeneric.td
===================================================================
--- lib/Target/Mips/MipsScheduleGeneric.td
+++ lib/Target/Mips/MipsScheduleGeneric.td
@@ -392,7 +392,7 @@
 //
 // c.<cc>.[ds], bc1[tf], bc1[tf]l
 def : ItinRW<[GenericWriteFPUCmp], [II_C_CC_D, II_C_CC_S, II_BC1F, II_BC1T,
-                                    II_BC1FL, II_BC1TL]>;
+                                    II_BC1FL, II_BC1TL, II_BC2F, II_BC2T]>;
 
 def : ItinRW<[GenericWriteFPUCmp], [II_CMP_CC_D, II_CMP_CC_S]>;
 
Index: lib/Target/Mips/MipsScheduleP5600.td
===================================================================
--- lib/Target/Mips/MipsScheduleP5600.td
+++ lib/Target/Mips/MipsScheduleP5600.td
@@ -544,7 +544,8 @@
 
 // bc1[ft], cfc1, mfc1, mfhc1, movf, movt
 def : ItinRW<[P5600WriteMoveFPUToGPR],
-             [II_BC1F, II_BC1FL, II_BC1T, II_BC1TL, II_CFC1, II_MFC1, II_MFHC1, II_MOVF, II_MOVT]>;
+             [II_BC1F, II_BC1FL, II_BC1T, II_BC1TL, II_BC2T, II_BC2F, II_CFC1,
+              II_MFC1, II_MFHC1, II_MOVF, II_MOVT]>;
 
 // swc1, swxc1, st.[bhwd]
 def : ItinRW<[P5600WriteStoreFPUS], [II_SDC1, II_SDXC1, II_SUXC1, II_SWC1,
Index: test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
+++ test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
@@ -16,6 +16,10 @@
 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
 0x01 0x00 0x01 0x45 # CHECK: bc1t 8
 0x00 0x00 0x00 0x00 # CHECK: nop
+0x4d 0x01 0x00 0x49 # CHECK: bc2f 1336
+0x4d 0x01 0x1c 0x49 # CHECK: bc2f $fcc7, 1336
+0x4d 0x01 0x01 0x49 # CHECK: bc2t 1336
+0x4d 0x01 0x1d 0x49 # CHECK: bc2t $fcc7, 1336
 0x9b 0x14 0x11 0x04 # CHECK: bal 21104
 0x00 0x00 0x00 0x00 # CHECK: nop
 0x9b 0x14 0x11 0x04 # CHECK: bal 21104
Index: test/MC/Disassembler/Mips/mips1/valid-mips1.txt
===================================================================
--- test/MC/Disassembler/Mips/mips1/valid-mips1.txt
+++ test/MC/Disassembler/Mips/mips1/valid-mips1.txt
@@ -96,6 +96,10 @@
 0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28
 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
+0x49 0x00 0x01 0x4d # CHECK: bc2f 1336
+0x49 0x1c 0x01 0x4d # CHECK: bc2f $fcc7, 1336
+0x49 0x01 0x01 0x4d # CHECK: bc2t 1336
+0x49 0x1d 0x01 0x4d # CHECK: bc2t $fcc7, 1336
 0x81 0x58 0xc7 0x4d # CHECK: lb $24, -14515($10)
 0x86 0xab 0xde 0x94 # CHECK: lh $11, -8556($21)
 0x89 0xf4 0xef 0x79 # CHECK: lwl $20, -4231($15)
Index: test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
+++ test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
@@ -17,6 +17,10 @@
 0x0c 0x00 0x02 0x45 # CHECK: bc1fl 52
 0x01 0x00 0x01 0x45 # CHECK: bc1t 8
 0xf4 0xf7 0x03 0x45 # CHECK: bc1tl -8236
+0x4d 0x01 0x00 0x49 # CHECK: bc2f 1336
+0x4d 0x01 0x1c 0x49 # CHECK: bc2f $fcc7, 1336
+0x4d 0x01 0x01 0x49 # CHECK: bc2t 1336
+0x4d 0x01 0x1d 0x49 # CHECK: bc2t $fcc7, 1336
 0x9b 0x14 0x11 0x04 # CHECK: bal 21104
 0x00 0x00 0x00 0x00 # CHECK: nop
 0x9b 0x14 0xd0 0x04 # CHECK: bltzal $6, 21104
Index: test/MC/Disassembler/Mips/mips2/valid-mips2.txt
===================================================================
--- test/MC/Disassembler/Mips/mips2/valid-mips2.txt
+++ test/MC/Disassembler/Mips/mips2/valid-mips2.txt
@@ -146,6 +146,10 @@
 0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28
 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
+0x49 0x00 0x01 0x4d # CHECK: bc2f 1336
+0x49 0x1c 0x01 0x4d # CHECK: bc2f $fcc7, 1336
+0x49 0x01 0x01 0x4d # CHECK: bc2t 1336
+0x49 0x1d 0x01 0x4d # CHECK: bc2t $fcc7, 1336
 0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548
 0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108
 0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976
Index: test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
+++ test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
@@ -17,6 +17,10 @@
 0x0c 0x00 0x02 0x45 # CHECK: bc1fl 52
 0x01 0x00 0x01 0x45 # CHECK: bc1t 8
 0xf4 0xf7 0x03 0x45 # CHECK: bc1tl -8236
+0x4d 0x01 0x00 0x49 # CHECK: bc2f 1336
+0x4d 0x01 0x1c 0x49 # CHECK: bc2f $fcc7, 1336
+0x4d 0x01 0x01 0x49 # CHECK: bc2t 1336
+0x4d 0x01 0x1d 0x49 # CHECK: bc2t $fcc7, 1336
 0x9b 0x14 0x11 0x04 # CHECK: bal 21104
 0x00 0x00 0x00 0x00 # CHECK: nop
 0x9b 0x14 0xd0 0x04 # CHECK: bltzal $6, 21104
Index: test/MC/Disassembler/Mips/mips3/valid-mips3.txt
===================================================================
--- test/MC/Disassembler/Mips/mips3/valid-mips3.txt
+++ test/MC/Disassembler/Mips/mips3/valid-mips3.txt
@@ -193,6 +193,10 @@
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
 0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
 0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
+0x49 0x00 0x01 0x4d # CHECK: bc2f 1336
+0x49 0x1c 0x01 0x4d # CHECK: bc2f $fcc7, 1336
+0x49 0x01 0x01 0x4d # CHECK: bc2t 1336
+0x49 0x1d 0x01 0x4d # CHECK: bc2t $fcc7, 1336
 0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548
 0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108
 0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976
Index: test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
+++ test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
@@ -16,6 +16,10 @@
 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
+0x4d 0x01 0x00 0x49 # CHECK: bc2f 1336
+0x4d 0x01 0x1c 0x49 # CHECK: bc2f $fcc7, 1336
+0x4d 0x01 0x01 0x49 # CHECK: bc2t 1336
+0x4d 0x01 0x1d 0x49 # CHECK: bc2t $fcc7, 1336
 0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
 0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
 0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
Index: test/MC/Disassembler/Mips/mips32/valid-mips32.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32/valid-mips32.txt
+++ test/MC/Disassembler/Mips/mips32/valid-mips32.txt
@@ -272,6 +272,10 @@
 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
+0x49 0x00 0x01 0x4d # CHECK: bc2f 1336
+0x49 0x1c 0x01 0x4d # CHECK: bc2f $fcc7, 1336
+0x49 0x01 0x01 0x4d # CHECK: bc2t 1336
+0x49 0x1d 0x01 0x4d # CHECK: bc2t $fcc7, 1336
 0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548
 0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108
 0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976
Index: test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
+++ test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
@@ -17,6 +17,10 @@
 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
+0x4d 0x01 0x00 0x49 # CHECK: bc2f 1336
+0x4d 0x01 0x1c 0x49 # CHECK: bc2f $fcc7, 1336
+0x4d 0x01 0x01 0x49 # CHECK: bc2t 1336
+0x4d 0x01 0x1d 0x49 # CHECK: bc2t $fcc7, 1336
 0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
 0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
 0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
Index: test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
+++ test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
@@ -290,6 +290,10 @@
 0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
 0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
 0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
+0x49 0x00 0x01 0x4d # CHECK: bc2f 1336
+0x49 0x1c 0x01 0x4d # CHECK: bc2f $fcc7, 1336
+0x49 0x01 0x01 0x4d # CHECK: bc2t 1336
+0x49 0x1d 0x01 0x4d # CHECK: bc2t $fcc7, 1336
 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
Index: test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
+++ test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
@@ -14,6 +14,10 @@
 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
+0x4d 0x01 0x00 0x49 # CHECK: bc2f 1336
+0x4d 0x01 0x1c 0x49 # CHECK: bc2f $fcc7, 1336
+0x4d 0x01 0x01 0x49 # CHECK: bc2t 1336
+0x4d 0x01 0x1d 0x49 # CHECK: bc2t $fcc7, 1336
 0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
 0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
 0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
Index: test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
+++ test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
@@ -287,6 +287,10 @@
 0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
 0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
 0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
+0x49 0x00 0x01 0x4d # CHECK: bc2f 1336
+0x49 0x1c 0x01 0x4d # CHECK: bc2f $fcc7, 1336
+0x49 0x01 0x01 0x4d # CHECK: bc2t 1336
+0x49 0x1d 0x01 0x4d # CHECK: bc2t $fcc7, 1336
 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
Index: test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
+++ test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
@@ -14,6 +14,10 @@
 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
+0x4d 0x01 0x00 0x49 # CHECK: bc2f 1336
+0x4d 0x01 0x1c 0x49 # CHECK: bc2f $fcc7, 1336
+0x4d 0x01 0x01 0x49 # CHECK: bc2t 1336
+0x4d 0x01 0x1d 0x49 # CHECK: bc2t $fcc7, 1336
 0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
 0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
 0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
Index: test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
+++ test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
@@ -288,6 +288,10 @@
 0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
 0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
 0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
+0x49 0x00 0x01 0x4d # CHECK: bc2f 1336
+0x49 0x1c 0x01 0x4d # CHECK: bc2f $fcc7, 1336
+0x49 0x01 0x01 0x4d # CHECK: bc2t 1336
+0x49 0x1d 0x01 0x4d # CHECK: bc2t $fcc7, 1336
 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
Index: test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
+++ test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
@@ -21,6 +21,10 @@
 0x00 0x00 0x05 0x45 # CHECK: bc1t $fcc1, 4
 0xf4 0xf7 0x03 0x45 # CHECK: bc1tl -8236
 0x06 0x00 0x1f 0x45 # CHECK: bc1tl $fcc7, 28
+0x4d 0x01 0x00 0x49 # CHECK: bc2f 1336
+0x4d 0x01 0x1c 0x49 # CHECK: bc2f $fcc7, 1336
+0x4d 0x01 0x01 0x49 # CHECK: bc2t 1336
+0x4d 0x01 0x1d 0x49 # CHECK: bc2t $fcc7, 1336
 0x9b 0x14 0x11 0x04 # CHECK: bal 21104
 0x00 0x00 0x00 0x00 # CHECK: nop
 0x9b 0x14 0xd0 0x04 # CHECK: bltzal $6, 21104
Index: test/MC/Disassembler/Mips/mips4/valid-mips4.txt
===================================================================
--- test/MC/Disassembler/Mips/mips4/valid-mips4.txt
+++ test/MC/Disassembler/Mips/mips4/valid-mips4.txt
@@ -209,6 +209,10 @@
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
 0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
 0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
+0x49 0x00 0x01 0x4d # CHECK: bc2f 1336
+0x49 0x1c 0x01 0x4d # CHECK: bc2f $fcc7, 1336
+0x49 0x01 0x01 0x4d # CHECK: bc2t 1336
+0x49 0x1d 0x01 0x4d # CHECK: bc2t $fcc7, 1336
 0x4c 0x20 0x01 0x01 # CHECK: ldxc1 $f4, $zero($1)          
 0x4c 0x21 0x00 0x28 # CHECK: msub.s $f0, $f1, $f0, $f1      
 0x4d 0xca 0x58 0x09 # CHECK: sdxc1 $f11, $10($14)
Index: test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
+++ test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
@@ -14,6 +14,10 @@
 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
+0x4d 0x01 0x00 0x49 # CHECK: bc2f 1336
+0x4d 0x01 0x1c 0x49 # CHECK: bc2f $fcc7, 1336
+0x4d 0x01 0x01 0x49 # CHECK: bc2t 1336
+0x4d 0x01 0x1d 0x49 # CHECK: bc2t $fcc7, 1336
 0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
 0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
 0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
Index: test/MC/Disassembler/Mips/mips64/valid-mips64.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64/valid-mips64.txt
+++ test/MC/Disassembler/Mips/mips64/valid-mips64.txt
@@ -337,6 +337,10 @@
 0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0           
 0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0              
+0x49 0x00 0x01 0x4d # CHECK: bc2f 1336
+0x49 0x1c 0x01 0x4d # CHECK: bc2f $fcc7, 1336
+0x49 0x01 0x01 0x4d # CHECK: bc2t 1336
+0x49 0x1d 0x01 0x4d # CHECK: bc2t $fcc7, 1336
 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12    
 0x4d 0xbb 0x0d 0xe0 # CHECK: madd.s $f23, $f13, $f1, $f27   
 0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548
Index: test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
+++ test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
@@ -18,6 +18,10 @@
 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
+0x4d 0x01 0x00 0x49 # CHECK: bc2f 1336
+0x4d 0x01 0x1c 0x49 # CHECK: bc2f $fcc7, 1336
+0x4d 0x01 0x01 0x49 # CHECK: bc2t 1336
+0x4d 0x01 0x1d 0x49 # CHECK: bc2t $fcc7, 1336
 0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
 0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
 0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
Index: test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
+++ test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
@@ -355,6 +355,10 @@
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
 0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0           
 0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0              
+0x49 0x00 0x01 0x4d # CHECK: bc2f 1336
+0x49 0x1c 0x01 0x4d # CHECK: bc2f $fcc7, 1336
+0x49 0x01 0x01 0x4d # CHECK: bc2t 1336
+0x49 0x1d 0x01 0x4d # CHECK: bc2t $fcc7, 1336
 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12    
 0x4d 0xbb 0x0d 0xe0 # CHECK: madd.s $f23, $f13, $f1, $f27   
 0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548
Index: test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
+++ test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
@@ -15,6 +15,10 @@
 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
+0x4d 0x01 0x00 0x49 # CHECK: bc2f 1336
+0x4d 0x01 0x1c 0x49 # CHECK: bc2f $fcc7, 1336
+0x4d 0x01 0x01 0x49 # CHECK: bc2t 1336
+0x4d 0x01 0x1d 0x49 # CHECK: bc2t $fcc7, 1336
 0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
 0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
 0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
Index: test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
+++ test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
@@ -357,6 +357,10 @@
 0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0
 0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0
+0x49 0x00 0x01 0x4d # CHECK: bc2f 1336
+0x49 0x1c 0x01 0x4d # CHECK: bc2f $fcc7, 1336
+0x49 0x01 0x01 0x4d # CHECK: bc2t 1336
+0x49 0x1d 0x01 0x4d # CHECK: bc2t $fcc7, 1336
 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12    
 0x4d 0xbb 0x0d 0xe0 # CHECK: madd.s $f23, $f13, $f1, $f27   
 0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548
Index: test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
+++ test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
@@ -15,6 +15,10 @@
 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
+0x4d 0x01 0x00 0x49 # CHECK: bc2f 1336
+0x4d 0x01 0x1c 0x49 # CHECK: bc2f $fcc7, 1336
+0x4d 0x01 0x01 0x49 # CHECK: bc2t 1336
+0x4d 0x01 0x1d 0x49 # CHECK: bc2t $fcc7, 1336
 0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
 0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
 0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
Index: test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
+++ test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
@@ -357,6 +357,10 @@
 0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0           
 0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0              
+0x49 0x00 0x01 0x4d # CHECK: bc2f 1336
+0x49 0x1c 0x01 0x4d # CHECK: bc2f $fcc7, 1336
+0x49 0x01 0x01 0x4d # CHECK: bc2t 1336
+0x49 0x1d 0x01 0x4d # CHECK: bc2t $fcc7, 1336
 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12    
 0x4d 0xbb 0x0d 0xe0 # CHECK: madd.s $f23, $f13, $f1, $f27   
 0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548
Index: test/MC/Mips/micromips/valid.s
===================================================================
--- test/MC/Mips/micromips/valid.s
+++ test/MC/Mips/micromips/valid.s
@@ -244,8 +244,8 @@
 c.un.s   $fcc1, $f30, $f4   # CHECK: c.un.s   $fcc1, $f30, $f4  # encoding: [0x54,0x9e,0x20,0x7c]
 bc1t 8                      # CHECK: bc1t 8                     # encoding: [0x43,0xa0,0x00,0x04]
 bc1f 16                     # CHECK: bc1f 16                    # encoding: [0x43,0x80,0x00,0x08]
-bc1t $fcc1, 4               # CHECK: bc1t $fcc1, 4              # encoding: [0x43,0xa0,0x00,0x02]
-bc1f $fcc2, -20             # CHECK: bc1f $fcc2, -20            # encoding: [0x43,0x80,0xff,0xf6]
+bc1t $fcc1, 4               # CHECK: bc1t $fcc1, 4              # encoding: [0x43,0xa4,0x00,0x02]
+bc1f $fcc2, -20             # CHECK: bc1f $fcc2, -20            # encoding: [0x43,0x88,0xff,0xf6]
 sync                        # CHECK: sync                   # encoding: [0x00,0x00,0x6b,0x7c]
 sync 0                      # CHECK: sync 0                 # encoding: [0x00,0x00,0x6b,0x7c]
 sync 1                      # CHECK: sync 1                 # encoding: [0x00,0x01,0x6b,0x7c]
Index: test/MC/Mips/mips1/valid.s
===================================================================
--- test/MC/Mips/mips1/valid.s
+++ test/MC/Mips/mips1/valid.s
@@ -20,6 +20,10 @@
         bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1t      $fcc0, 4             # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
         bc1t      4                    # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc2f      $fcc0, 4             # CHECK: bc2f 4        # encoding: [0x49,0x00,0x00,0x01]
+        bc2f      4                    # CHECK: bc2f 4        # encoding: [0x49,0x00,0x00,0x01]
+        bc2t      $fcc0, 4             # CHECK: bc2t 4        # encoding: [0x49,0x01,0x00,0x01]
+        bc2t      4                    # CHECK: bc2t 4        # encoding: [0x49,0x01,0x00,0x01]
         bal       21100                # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
         bgezal    $0, 21100            # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
         bgezal    $6, 21100            # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
Index: test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s
===================================================================
--- test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s
+++ test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s
@@ -5,8 +5,6 @@
 # RUN: FileCheck %s < %t1
 
 	.set noat
-        bc2f      4                   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        bc2t      4                   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         lwl       $s4,-4231($15)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lwr       $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swl       $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Index: test/MC/Mips/mips32r6/invalid-mips1.s
===================================================================
--- test/MC/Mips/mips32r6/invalid-mips1.s
+++ test/MC/Mips/mips32r6/invalid-mips1.s
@@ -8,6 +8,8 @@
         add       $9,$14,15176        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         add       $24,-7193           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         addi      $13,$9,26322        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc2f      4                   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc2t      4                   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         c.ngl.d   $f29,$f29           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         c.ngle.d  $f0,$f16            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         c.sf.d    $f30,$f0            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Index: test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s
===================================================================
--- test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s
+++ test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s
@@ -6,10 +6,6 @@
 # RUN: FileCheck %s < %t1
 
         .set noat
-        bc2f  4                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        bc2f  $fcc0,4           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        bc2t  4                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        bc2t  $fcc0,4           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         bc2tl 4                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         bc2tl $fcc1,4           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         bc2fl 4                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
Index: test/MC/Mips/mips32r6/invalid-mips32.s
===================================================================
--- test/MC/Mips/mips32r6/invalid-mips32.s
+++ test/MC/Mips/mips32r6/invalid-mips32.s
@@ -5,8 +5,12 @@
 # RUN: FileCheck %s < %t1
 
         .set noat
-        bc1fl     $fcc7,27            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        bc1tl     $fcc7,27            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc1fl     $fcc7,27      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc1tl     $fcc7,27      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc2f      4             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc2f      $fcc0,4       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc2t      4             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc2t      $fcc0,4       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         madd      $s6,$13       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         madd      $zero,$9      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         maddu     $s3,$gp       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Index: test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s
===================================================================
--- test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s
+++ test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s
@@ -5,8 +5,6 @@
 # RUN: FileCheck %s < %t1
 
 	.set noat
-        bc2f      4                   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        bc2t      4                   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         lwl       $s4,-4231($15)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lwr       $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swl       $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Index: test/MC/Mips/mips64r6/invalid-mips1.s
===================================================================
--- test/MC/Mips/mips64r6/invalid-mips1.s
+++ test/MC/Mips/mips64r6/invalid-mips1.s
@@ -8,6 +8,8 @@
         add       $9,$14,15176        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         add       $24,-7193           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         addi      $13,$9,26322        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc2f      4                   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc2t      4                   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bgezal    $0, 21100           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bgezal    $6, 21100           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bltzal    $6, 21100           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Index: test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s
===================================================================
--- test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s
+++ test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s
@@ -6,11 +6,7 @@
 # RUN: FileCheck %s < %t1
 
         .set noat
-        bc2f  $fcc0,4           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        bc2f  4                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         bc2fl $fcc1,4           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         bc2fl 4                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        bc2t  $fcc0,4           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        bc2t  4                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         bc2tl $fcc1,4           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         bc2tl 4                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
Index: test/MC/Mips/mips64r6/invalid-mips32.s
===================================================================
--- /dev/null
+++ test/MC/Mips/mips64r6/invalid-mips32.s
@@ -0,0 +1,11 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 \
+# RUN:     2>&1 | FileCheck %s
+
+
+        .set noat
+        bc2f  $fcc0,4           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc2f  4                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc2t  $fcc0,4           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc2t  4                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled