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Differential D6014

[mips] MIPS Branch on Coprocessor 2 Instructions
Needs RevisionPublic

Authored by sdardis on Oct 28 2014, 8:09 AM.

Details

Reviewers
ipetkovic
sdardis
zoran.jovanovic
seanbruno
dsanders
Summary

This patch adds support for the BC2F and BC2T MIPS instructions. Besides the
support, corresponding assembler and dissasembler tests are also added.

Patch By: Igor Petkovic

Contributions from: Simon Dardis

Diff Detail

Event Timeline

ipetkovic updated this revision to Diff 15524.Oct 28 2014, 8:09 AM
ipetkovic retitled this revision from to [mips] MIPS Branch on Coprocessor 2 Instructions.
ipetkovic updated this object.
ipetkovic edited the test plan for this revision. (Show Details)
ipetkovic added reviewers: zoran.jovanovic, dsanders.
ipetkovic added a subscriber: petarj.
dsanders requested changes to this revision.Nov 3 2014, 3:36 AM
dsanders edited edge metadata.

Could you bring back the tests you deleted as explained below.

Other than that, there's just the one nit.

lib/Target/Mips/MipsInstrFormats.td
753

I'd prefer to have a separate BC2F_FM class.

test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s
8–9

These tests should be moved to the invalid-mips1.s test if they now produce the correct error message. At the moment, you seem to have deleted the test.

Similarly for the other invalid*.s tests

This revision now requires changes to proceed.Nov 3 2014, 3:36 AM
ipetkovic updated this revision to Diff 15801.Nov 5 2014, 2:11 AM
ipetkovic edited edge metadata.

Nits are fixed and tests are returned and moved in to right files.

dsanders accepted this revision.Nov 5 2014, 7:27 AM
dsanders edited edge metadata.

Thanks. LGTM

This revision is now accepted and ready to land.Nov 5 2014, 7:27 AM
seanbruno requested changes to this revision.Sep 26 2016, 7:05 AM
seanbruno added a reviewer: seanbruno.
seanbruno added a subscriber: seanbruno.

This looks like it needs to be refreshed to a more current trunk if possible before its committed.

This revision now requires changes to proceed.Sep 26 2016, 7:05 AM
seanbruno added a reviewer: sdardis.Feb 1 2017, 7:33 AM
sdardis commandeered this revision.Feb 2 2017, 7:14 AM
sdardis edited reviewers, added: ipetkovic; removed: sdardis.
sdardis edited edge metadata.

Commandeering for update.

sdardis updated this revision to Diff 86806.Feb 2 2017, 7:16 AM
sdardis edited edge metadata.
sdardis edited the summary of this revision. (Show Details)

Updated to trunk. Added micromips versions of instructions.

sdardis updated this revision to Diff 86811.Feb 2 2017, 7:29 AM

Missed the Octeon exclusions from these instructions.

dsanders resigned from this revision.Jul 18 2019, 7:01 PM
This revision now requires changes to proceed.Jul 18 2019, 7:01 PM
Herald added subscribers: atanasyan, arichardson. · View Herald TranscriptJul 18 2019, 7:01 PM

Revision Contents

PathSize
lib/
Target/
Mips/
8 lines
14 lines
test/
MC/
Disassembler/
Mips/
12 lines
Mips/
mips1/
4 lines
mips32r6/
2 lines
2 lines
4 lines
4 lines
mips64r6/
2 lines
2 lines
4 lines
13 lines

Diff 15801

lib/Target/Mips/MipsInstrFPU.td

Show First 20 Lines • Show All 522 Lines • ▼ Show 20 Lines
def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>, def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>,
BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6; BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, IIBranch, MIPS_BRANCH_F, 0>, def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, IIBranch, MIPS_BRANCH_F, 0>,
BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6; BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, IIBranch, MIPS_BRANCH_T>, def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, IIBranch, MIPS_BRANCH_T>,
BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6; BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, IIBranch, MIPS_BRANCH_T, 0>, def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, IIBranch, MIPS_BRANCH_T, 0>,
BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6; BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
def BC2F : MMRel, BC1F_FT<"bc2f", brtarget, IIBranch, MIPS_BRANCH_F>,
BC2F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
def BC2T : MMRel, BC1F_FT<"bc2t", brtarget, IIBranch, MIPS_BRANCH_T>,
BC2F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Floating Point Flag Conditions // Floating Point Flag Conditions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h. // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
// They must be kept in synch. // They must be kept in synch.
def MIPS_FCOND_F : PatLeaf<(i32 0)>; def MIPS_FCOND_F : PatLeaf<(i32 0)>;
def MIPS_FCOND_UN : PatLeaf<(i32 1)>; def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>, def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>, def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>,
ISA_MIPS2_NOT_32R6_64R6; ISA_MIPS2_NOT_32R6_64R6;
def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>, def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>, def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>,
ISA_MIPS2_NOT_32R6_64R6; ISA_MIPS2_NOT_32R6_64R6;
def : MipsInstAlias<"bc2f $offset", (BC2F FCC0, brtarget:$offset)>,
ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"bc2t $offset", (BC2T FCC0, brtarget:$offset)>,
ISA_MIPS1_NOT_32R6_64R6;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Floating Point Patterns // Floating Point Patterns
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)), def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstrFormats.td

Show First 20 Lines • Show All 744 Lines • ▼ Show 20 Linesclass SWXC1_FM<bits<6> funct> : StdArch {
let Inst{31-26} = 0x13; let Inst{31-26} = 0x13;
let Inst{25-21} = base; let Inst{25-21} = base;
let Inst{20-16} = index; let Inst{20-16} = index;
let Inst{15-11} = fs; let Inst{15-11} = fs;
let Inst{10-6} = 0; let Inst{10-6} = 0;
let Inst{5-0} = funct; let Inst{5-0} = funct;
} }
class BC0F_FM<bit HasDelaySlot, bit tf> : StdArch { class BC0F_FM<bit HasDelaySlot, bit tf> : StdArch {
dsandersUnsubmitted
Not Done
ReplyInline Actions

I'd prefer to have a separate BC2F_FM class.

dsanders: I'd prefer to have a separate BC2F_FM class.
bits<3> fcc; bits<3> fcc;
bits<16> offset; bits<16> offset;
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0x10; let Inst{31-26} = 0x10;
let Inst{25-21} = 0x8; let Inst{25-21} = 0x8;
let Inst{20-18} = 0x0; let Inst{20-18} = 0x0;
Show All 11 Linesclass BC1F_FM<bit nd, bit tf> : StdArch {
let Inst{31-26} = 0x11; let Inst{31-26} = 0x11;
let Inst{25-21} = 0x8; let Inst{25-21} = 0x8;
let Inst{20-18} = fcc; let Inst{20-18} = fcc;
let Inst{17} = nd; let Inst{17} = nd;
let Inst{16} = tf; let Inst{16} = tf;
let Inst{15-0} = offset; let Inst{15-0} = offset;
} }
class BC2F_FM<bit nd, bit tf> : StdArch {
bits<3> fcc;
bits<16> offset;
bits<32> Inst;
let Inst{31-26} = 0x12;
let Inst{25-21} = 0x8;
let Inst{20-18} = fcc;
let Inst{17} = nd;
let Inst{16} = tf;
let Inst{15-0} = offset;
}
class CEQS_FM<bits<5> fmt> : StdArch { class CEQS_FM<bits<5> fmt> : StdArch {
bits<5> fs; bits<5> fs;
bits<5> ft; bits<5> ft;
bits<4> cond; bits<4> cond;
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0x11; let Inst{31-26} = 0x11;
▲ Show 20 Lines • Show All 132 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips32.txt

Show All 39 Lines
0x45 0x1c 0x01 0x4d 0x45 0x1c 0x01 0x4d
# CHECK: bc1t 1332 # CHECK: bc1t 1332
0x45 0x01 0x01 0x4d 0x45 0x01 0x01 0x4d
# CHECK: bc1t $fcc7, 1332 # CHECK: bc1t $fcc7, 1332
0x45 0x1d 0x01 0x4d 0x45 0x1d 0x01 0x4d
# CHECK: bc2f 1332
0x49 0x00 0x01 0x4d
# CHECK: bc2f $fcc7, 1332
0x49 0x1c 0x01 0x4d
# CHECK: bc2t 1332
0x49 0x01 0x01 0x4d
# CHECK: bc2t $fcc7, 1332
0x49 0x1d 0x01 0x4d
# CHECK: beq $9, $6, 1332 # CHECK: beq $9, $6, 1332
0x11 0x26 0x01 0x4d 0x11 0x26 0x01 0x4d
# CHECK: beql $9, $6, 1332 # CHECK: beql $9, $6, 1332
0x51 0x26 0x01 0x4d 0x51 0x26 0x01 0x4d
# CHECK: bgez $6, 1332 # CHECK: bgez $6, 1332
0x04 0xc1 0x01 0x4d 0x04 0xc1 0x01 0x4d
▲ Show 20 Lines • Show All 420 Lines • Show Last 20 Lines

test/MC/Mips/mips1/valid.s

Show All 16 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | FileCheck %s
and $s7,$v0,$12 and $s7,$v0,$12
and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
bc0f 4 # CHECK: bc0f 4 # encoding: [0x41,0x00,0x00,0x01] bc0f 4 # CHECK: bc0f 4 # encoding: [0x41,0x00,0x00,0x01]
bc0t 4 # CHECK: bc0t 4 # encoding: [0x41,0x01,0x00,0x01] bc0t 4 # CHECK: bc0t 4 # encoding: [0x41,0x01,0x00,0x01]
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
bc2f $fcc0, 4 # CHECK: bc2f 4 # encoding: [0x49,0x00,0x00,0x01]
bc2f 4 # CHECK: bc2f 4 # encoding: [0x49,0x00,0x00,0x01]
bc2t $fcc0, 4 # CHECK: bc2t 4 # encoding: [0x49,0x01,0x00,0x01]
bc2t 4 # CHECK: bc2t 4 # encoding: [0x49,0x01,0x00,0x01]
bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
c.ngl.d $f29,$f29 c.ngl.d $f29,$f29
c.ngle.d $f0,$f16 c.ngle.d $f0,$f16
c.sf.d $f30,$f0 c.sf.d $f30,$f0
c.sf.s $f14,$f22 c.sf.s $f14,$f22
▲ Show 20 Lines • Show All 88 Lines • Show Last 20 Lines

test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
dsandersUnsubmitted
Not Done
ReplyInline Actions

These tests should be moved to the invalid-mips1.s test if they now produce the correct error message. At the moment, you seem to have deleted the test.

Similarly for the other invalid*.s tests

dsanders: These tests should be moved to the invalid-mips1.s test if they now produce the correct error…
lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

test/MC/Mips/mips32r6/invalid-mips1.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
add $9,$14,15176 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled add $9,$14,15176 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
add $24,-7193 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled add $24,-7193 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
c.sf.d $f30,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.sf.d $f30,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
c.sf.s $f14,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.sf.s $f14,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mthi $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mthi $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Show All 10 Lines

test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s

# Instructions that are invalid and are correctly rejected but use the wrong # Instructions that are invalid and are correctly rejected but use the wrong
# error message at the moment. # error message at the moment.
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

test/MC/Mips/mips32r6/invalid-mips32.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

test/MC/Mips/mips64r6/invalid-mips1.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
add $9,$14,15176 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled add $9,$14,15176 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
add $24,-7193 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled add $24,-7193 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
c.sf.d $f30,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.sf.d $f30,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
c.sf.s $f14,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.sf.s $f14,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s

# Instructions that are invalid and are correctly rejected but use the wrong # Instructions that are invalid and are correctly rejected but use the wrong
# error message at the moment. # error message at the moment.
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

test/MC/Mips/mips64r6/invalid-mips32.s

  • This file was added.
# Instructions that are invalid
#
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 \
# RUN: 2>%t1
# RUN: FileCheck %s < %t1
.set noat
bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled