Index: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp +++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp @@ -1378,9 +1378,10 @@ static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned = false) { + auto *CImm = cast(Op->getOperand(ImmOp)); return DAG.getConstant( APInt(Op->getValueType(0).getScalarType().getSizeInBits(), - Op->getConstantOperandVal(ImmOp), IsSigned), + IsSigned ? CImm->getSExtValue() : CImm->getZExtValue(), IsSigned), SDLoc(Op), Op->getValueType(0)); } Index: llvm/trunk/test/CodeGen/Mips/msa/i10.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/msa/i10.ll +++ llvm/trunk/test/CodeGen/Mips/msa/i10.ll @@ -87,3 +87,74 @@ ; CHECK-DAG: bnz.d [[R0]] ; CHECK: .size llvm_mips_bnz_d_test +@llvm_mips_ldi_b_RES1 = global <16 x i8> , align 16 +@llvm_mips_ldi_b_RES2 = global <16 x i8> , align 16 + +define void @llvm_mips_ldi_b_test() nounwind { +entry: + %0 = call <16 x i8> @llvm.mips.ldi.b(i32 3) + store <16 x i8> %0, <16 x i8>* @llvm_mips_ldi_b_RES1 + %1 = call <16 x i8> @llvm.mips.ldi.b(i32 -3) + store <16 x i8> %1, <16 x i8>* @llvm_mips_ldi_b_RES2 + ret void +} + +declare <16 x i8> @llvm.mips.ldi.b(i32) + +; CHECK-LABEL: llvm_mips_ldi_b_test +; CHECK-DAG: ldi.b {{\$w[0-9]}}, 3 +; CHECK-DAG: ldi.b {{\$w[0-9]}}, -3 + +@llvm_mips_ldi_h_RES1 = global <8 x i16> , align 16 +@llvm_mips_ldi_h_RES2 = global <8 x i16> , align 16 + +define void @llvm_mips_ldi_h_test() nounwind { +entry: + %0 = call <8 x i16> @llvm.mips.ldi.h(i32 3) + store <8 x i16> %0, <8 x i16>* @llvm_mips_ldi_h_RES1 + %1 = call <8 x i16> @llvm.mips.ldi.h(i32 -3) + store <8 x i16> %1, <8 x i16>* @llvm_mips_ldi_h_RES2 + ret void +} + +declare <8 x i16> @llvm.mips.ldi.h(i32) + +; CHECK-LABEL: llvm_mips_ldi_h_test +; CHECK-DAG: ldi.h {{\$w[0-9]}}, 3 +; CHECK-DAG: ldi.h {{\$w[0-9]}}, -3 + +@llvm_mips_ldi_w_RES1 = global <4 x i32> , align 16 +@llvm_mips_ldi_w_RES2 = global <4 x i32> , align 16 + +define void @llvm_mips_ldi_w_test() nounwind { +entry: + %0 = call <4 x i32> @llvm.mips.ldi.w(i32 3) + store <4 x i32> %0, <4 x i32>* @llvm_mips_ldi_w_RES1 + %1 = call <4 x i32> @llvm.mips.ldi.w(i32 -3) + store <4 x i32> %1, <4 x i32>* @llvm_mips_ldi_w_RES2 + ret void +} + +declare <4 x i32> @llvm.mips.ldi.w(i32) + +; CHECK-LABEL: llvm_mips_ldi_w_test +; CHECK-DAG: ldi.w {{\$w[0-9]}}, 3 +; CHECK-DAG: ldi.w {{\$w[0-9]}}, -3 + +@llvm_mips_ldi_d_RES1 = global <2 x i64> , align 16 +@llvm_mips_ldi_d_RES2 = global <2 x i64> , align 16 + +define void @llvm_mips_ldi_d_test() nounwind { +entry: + %0 = call <2 x i64> @llvm.mips.ldi.d(i32 3) + store <2 x i64> %0, <2 x i64>* @llvm_mips_ldi_d_RES1 + %1 = call <2 x i64> @llvm.mips.ldi.d(i32 -3) + store <2 x i64> %1, <2 x i64>* @llvm_mips_ldi_d_RES2 + ret void +} + +declare <2 x i64> @llvm.mips.ldi.d(i32) + +; CHECK-LABEL: llvm_mips_ldi_d_test +; CHECK-DAG: ldi.d {{\$w[0-9]}}, 3 +; CHECK-DAG: ldi.d {{\$w[0-9]}}, -3 Index: llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll +++ llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll @@ -5,155 +5,195 @@ ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_ceqi_b_ARG1 = global <16 x i8> , align 16 -@llvm_mips_ceqi_b_RES = global <16 x i8> , align 16 +@llvm_mips_ceqi_b_RES1 = global <16 x i8> , align 16 +@llvm_mips_ceqi_b_RES2 = global <16 x i8> , align 16 define void @llvm_mips_ceqi_b_test() nounwind { entry: %0 = load <16 x i8>, <16 x i8>* @llvm_mips_ceqi_b_ARG1 %1 = tail call <16 x i8> @llvm.mips.ceqi.b(<16 x i8> %0, i32 14) - store <16 x i8> %1, <16 x i8>* @llvm_mips_ceqi_b_RES + store <16 x i8> %1, <16 x i8>* @llvm_mips_ceqi_b_RES1 + %2 = tail call <16 x i8> @llvm.mips.ceqi.b(<16 x i8> %0, i32 -14) + store <16 x i8> %2, <16 x i8>* @llvm_mips_ceqi_b_RES2 ret void } declare <16 x i8> @llvm.mips.ceqi.b(<16 x i8>, i32) nounwind ; CHECK: llvm_mips_ceqi_b_test: -; CHECK: ld.b -; CHECK: ceqi.b -; CHECK: st.b +; CHECK: ld.b [[RS:\$w[0-9]+]] +; CHECK: ceqi.b [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.b [[RD1]] +; CHECK: ceqi.b [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.b [[RD2]] ; CHECK: .size llvm_mips_ceqi_b_test ; @llvm_mips_ceqi_h_ARG1 = global <8 x i16> , align 16 -@llvm_mips_ceqi_h_RES = global <8 x i16> , align 16 +@llvm_mips_ceqi_h_RES1 = global <8 x i16> , align 16 +@llvm_mips_ceqi_h_RES2 = global <8 x i16> , align 16 define void @llvm_mips_ceqi_h_test() nounwind { entry: %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ceqi_h_ARG1 %1 = tail call <8 x i16> @llvm.mips.ceqi.h(<8 x i16> %0, i32 14) - store <8 x i16> %1, <8 x i16>* @llvm_mips_ceqi_h_RES + store <8 x i16> %1, <8 x i16>* @llvm_mips_ceqi_h_RES1 + %2 = tail call <8 x i16> @llvm.mips.ceqi.h(<8 x i16> %0, i32 -14) + store <8 x i16> %2, <8 x i16>* @llvm_mips_ceqi_h_RES2 ret void } declare <8 x i16> @llvm.mips.ceqi.h(<8 x i16>, i32) nounwind ; CHECK: llvm_mips_ceqi_h_test: -; CHECK: ld.h -; CHECK: ceqi.h -; CHECK: st.h +; CHECK: ld.h [[RS:\$w[0-9]+]] +; CHECK: ceqi.h [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.h [[RD1]] +; CHECK: ceqi.h [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.h [[RD2]] ; CHECK: .size llvm_mips_ceqi_h_test ; @llvm_mips_ceqi_w_ARG1 = global <4 x i32> , align 16 -@llvm_mips_ceqi_w_RES = global <4 x i32> , align 16 +@llvm_mips_ceqi_w_RES1 = global <4 x i32> , align 16 +@llvm_mips_ceqi_w_RES2 = global <4 x i32> , align 16 define void @llvm_mips_ceqi_w_test() nounwind { entry: %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ceqi_w_ARG1 %1 = tail call <4 x i32> @llvm.mips.ceqi.w(<4 x i32> %0, i32 14) - store <4 x i32> %1, <4 x i32>* @llvm_mips_ceqi_w_RES + store <4 x i32> %1, <4 x i32>* @llvm_mips_ceqi_w_RES1 + %2 = tail call <4 x i32> @llvm.mips.ceqi.w(<4 x i32> %0, i32 -14) + store <4 x i32> %2, <4 x i32>* @llvm_mips_ceqi_w_RES2 ret void } declare <4 x i32> @llvm.mips.ceqi.w(<4 x i32>, i32) nounwind ; CHECK: llvm_mips_ceqi_w_test: -; CHECK: ld.w -; CHECK: ceqi.w -; CHECK: st.w +; CHECK: ld.w [[RS:\$w[0-9]+]] +; CHECK: ceqi.w [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.w [[RD1]] +; CHECK: ceqi.w [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.w [[RD2]] ; CHECK: .size llvm_mips_ceqi_w_test ; @llvm_mips_ceqi_d_ARG1 = global <2 x i64> , align 16 -@llvm_mips_ceqi_d_RES = global <2 x i64> , align 16 +@llvm_mips_ceqi_d_RES1 = global <2 x i64> , align 16 +@llvm_mips_ceqi_d_RES2 = global <2 x i64> , align 16 define void @llvm_mips_ceqi_d_test() nounwind { entry: %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ceqi_d_ARG1 %1 = tail call <2 x i64> @llvm.mips.ceqi.d(<2 x i64> %0, i32 14) - store <2 x i64> %1, <2 x i64>* @llvm_mips_ceqi_d_RES + store <2 x i64> %1, <2 x i64>* @llvm_mips_ceqi_d_RES1 + %2 = tail call <2 x i64> @llvm.mips.ceqi.d(<2 x i64> %0, i32 -14) + store <2 x i64> %2, <2 x i64>* @llvm_mips_ceqi_d_RES2 ret void } declare <2 x i64> @llvm.mips.ceqi.d(<2 x i64>, i32) nounwind ; CHECK: llvm_mips_ceqi_d_test: -; CHECK: ld.d -; CHECK: ceqi.d -; CHECK: st.d +; CHECK: ld.d [[RS:\$w[0-9]+]] +; CHECK: ceqi.d [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.d [[RD1]] +; CHECK: ceqi.d [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.d [[RD2]] ; CHECK: .size llvm_mips_ceqi_d_test ; @llvm_mips_clei_s_b_ARG1 = global <16 x i8> , align 16 -@llvm_mips_clei_s_b_RES = global <16 x i8> , align 16 +@llvm_mips_clei_s_b_RES1 = global <16 x i8> , align 16 +@llvm_mips_clei_s_b_RES2 = global <16 x i8> , align 16 define void @llvm_mips_clei_s_b_test() nounwind { entry: %0 = load <16 x i8>, <16 x i8>* @llvm_mips_clei_s_b_ARG1 %1 = tail call <16 x i8> @llvm.mips.clei.s.b(<16 x i8> %0, i32 14) - store <16 x i8> %1, <16 x i8>* @llvm_mips_clei_s_b_RES + store <16 x i8> %1, <16 x i8>* @llvm_mips_clei_s_b_RES1 + %2 = tail call <16 x i8> @llvm.mips.clei.s.b(<16 x i8> %0, i32 -14) + store <16 x i8> %2, <16 x i8>* @llvm_mips_clei_s_b_RES2 ret void } declare <16 x i8> @llvm.mips.clei.s.b(<16 x i8>, i32) nounwind ; CHECK: llvm_mips_clei_s_b_test: -; CHECK: ld.b -; CHECK: clei_s.b -; CHECK: st.b +; CHECK: ld.b [[RS:\$w[0-9]+]] +; CHECK: clei_s.b [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.b [[RD1]] +; CHECK: clei_s.b [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.b [[RD2]] ; CHECK: .size llvm_mips_clei_s_b_test ; @llvm_mips_clei_s_h_ARG1 = global <8 x i16> , align 16 -@llvm_mips_clei_s_h_RES = global <8 x i16> , align 16 +@llvm_mips_clei_s_h_RES1 = global <8 x i16> , align 16 +@llvm_mips_clei_s_h_RES2 = global <8 x i16> , align 16 define void @llvm_mips_clei_s_h_test() nounwind { entry: %0 = load <8 x i16>, <8 x i16>* @llvm_mips_clei_s_h_ARG1 %1 = tail call <8 x i16> @llvm.mips.clei.s.h(<8 x i16> %0, i32 14) - store <8 x i16> %1, <8 x i16>* @llvm_mips_clei_s_h_RES + store <8 x i16> %1, <8 x i16>* @llvm_mips_clei_s_h_RES1 + %2 = tail call <8 x i16> @llvm.mips.clei.s.h(<8 x i16> %0, i32 -14) + store <8 x i16> %2, <8 x i16>* @llvm_mips_clei_s_h_RES2 ret void } declare <8 x i16> @llvm.mips.clei.s.h(<8 x i16>, i32) nounwind ; CHECK: llvm_mips_clei_s_h_test: -; CHECK: ld.h -; CHECK: clei_s.h -; CHECK: st.h +; CHECK: ld.h [[RS:\$w[0-9]+]] +; CHECK: clei_s.h [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.h [[RD1]] +; CHECK: clei_s.h [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.h [[RD2]] ; CHECK: .size llvm_mips_clei_s_h_test ; @llvm_mips_clei_s_w_ARG1 = global <4 x i32> , align 16 -@llvm_mips_clei_s_w_RES = global <4 x i32> , align 16 +@llvm_mips_clei_s_w_RES1 = global <4 x i32> , align 16 +@llvm_mips_clei_s_w_RES2 = global <4 x i32> , align 16 define void @llvm_mips_clei_s_w_test() nounwind { entry: %0 = load <4 x i32>, <4 x i32>* @llvm_mips_clei_s_w_ARG1 %1 = tail call <4 x i32> @llvm.mips.clei.s.w(<4 x i32> %0, i32 14) - store <4 x i32> %1, <4 x i32>* @llvm_mips_clei_s_w_RES + store <4 x i32> %1, <4 x i32>* @llvm_mips_clei_s_w_RES1 + %2 = tail call <4 x i32> @llvm.mips.clei.s.w(<4 x i32> %0, i32 -14) + store <4 x i32> %2, <4 x i32>* @llvm_mips_clei_s_w_RES2 ret void } declare <4 x i32> @llvm.mips.clei.s.w(<4 x i32>, i32) nounwind ; CHECK: llvm_mips_clei_s_w_test: -; CHECK: ld.w -; CHECK: clei_s.w -; CHECK: st.w +; CHECK: ld.w [[RS:\$w[0-9]+]] +; CHECK: clei_s.w [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.w [[RD1]] +; CHECK: clei_s.w [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.w [[RD2]] ; CHECK: .size llvm_mips_clei_s_w_test ; @llvm_mips_clei_s_d_ARG1 = global <2 x i64> , align 16 -@llvm_mips_clei_s_d_RES = global <2 x i64> , align 16 +@llvm_mips_clei_s_d_RES1 = global <2 x i64> , align 16 +@llvm_mips_clei_s_d_RES2 = global <2 x i64> , align 16 define void @llvm_mips_clei_s_d_test() nounwind { entry: %0 = load <2 x i64>, <2 x i64>* @llvm_mips_clei_s_d_ARG1 %1 = tail call <2 x i64> @llvm.mips.clei.s.d(<2 x i64> %0, i32 14) - store <2 x i64> %1, <2 x i64>* @llvm_mips_clei_s_d_RES + store <2 x i64> %1, <2 x i64>* @llvm_mips_clei_s_d_RES1 + %2 = tail call <2 x i64> @llvm.mips.clei.s.d(<2 x i64> %0, i32 -14) + store <2 x i64> %2, <2 x i64>* @llvm_mips_clei_s_d_RES2 ret void } declare <2 x i64> @llvm.mips.clei.s.d(<2 x i64>, i32) nounwind ; CHECK: llvm_mips_clei_s_d_test: -; CHECK: ld.d -; CHECK: clei_s.d -; CHECK: st.d +; CHECK: ld.d [[RS:\$w[0-9]+]] +; CHECK: clei_s.d [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.d [[RD1]] +; CHECK: clei_s.d [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.d [[RD2]] ; CHECK: .size llvm_mips_clei_s_d_test ; @llvm_mips_clei_u_b_ARG1 = global <16 x i8> , align 16 @@ -233,79 +273,99 @@ ; CHECK: .size llvm_mips_clei_u_d_test ; @llvm_mips_clti_s_b_ARG1 = global <16 x i8> , align 16 -@llvm_mips_clti_s_b_RES = global <16 x i8> , align 16 +@llvm_mips_clti_s_b_RES1 = global <16 x i8> , align 16 +@llvm_mips_clti_s_b_RES2 = global <16 x i8> , align 16 define void @llvm_mips_clti_s_b_test() nounwind { entry: %0 = load <16 x i8>, <16 x i8>* @llvm_mips_clti_s_b_ARG1 %1 = tail call <16 x i8> @llvm.mips.clti.s.b(<16 x i8> %0, i32 14) - store <16 x i8> %1, <16 x i8>* @llvm_mips_clti_s_b_RES + store <16 x i8> %1, <16 x i8>* @llvm_mips_clti_s_b_RES1 + %2 = tail call <16 x i8> @llvm.mips.clti.s.b(<16 x i8> %0, i32 -14) + store <16 x i8> %2, <16 x i8>* @llvm_mips_clti_s_b_RES2 ret void } declare <16 x i8> @llvm.mips.clti.s.b(<16 x i8>, i32) nounwind ; CHECK: llvm_mips_clti_s_b_test: -; CHECK: ld.b -; CHECK: clti_s.b -; CHECK: st.b +; CHECK: ld.b [[RS:\$w[0-9]+]] +; CHECK: clti_s.b [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.b [[RD1]] +; CHECK: clti_s.b [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.b [[RD2]] ; CHECK: .size llvm_mips_clti_s_b_test ; @llvm_mips_clti_s_h_ARG1 = global <8 x i16> , align 16 -@llvm_mips_clti_s_h_RES = global <8 x i16> , align 16 +@llvm_mips_clti_s_h_RES1 = global <8 x i16> , align 16 +@llvm_mips_clti_s_h_RES2 = global <8 x i16> , align 16 define void @llvm_mips_clti_s_h_test() nounwind { entry: %0 = load <8 x i16>, <8 x i16>* @llvm_mips_clti_s_h_ARG1 %1 = tail call <8 x i16> @llvm.mips.clti.s.h(<8 x i16> %0, i32 14) - store <8 x i16> %1, <8 x i16>* @llvm_mips_clti_s_h_RES + store <8 x i16> %1, <8 x i16>* @llvm_mips_clti_s_h_RES1 + %2 = tail call <8 x i16> @llvm.mips.clti.s.h(<8 x i16> %0, i32 -14) + store <8 x i16> %2, <8 x i16>* @llvm_mips_clti_s_h_RES2 ret void } declare <8 x i16> @llvm.mips.clti.s.h(<8 x i16>, i32) nounwind ; CHECK: llvm_mips_clti_s_h_test: -; CHECK: ld.h -; CHECK: clti_s.h -; CHECK: st.h +; CHECK: ld.h [[RS:\$w[0-9]+]] +; CHECK: clti_s.h [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.h [[RD1]] +; CHECK: clti_s.h [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.h [[RD2]] ; CHECK: .size llvm_mips_clti_s_h_test ; @llvm_mips_clti_s_w_ARG1 = global <4 x i32> , align 16 -@llvm_mips_clti_s_w_RES = global <4 x i32> , align 16 +@llvm_mips_clti_s_w_RES1 = global <4 x i32> , align 16 +@llvm_mips_clti_s_w_RES2 = global <4 x i32> , align 16 define void @llvm_mips_clti_s_w_test() nounwind { entry: %0 = load <4 x i32>, <4 x i32>* @llvm_mips_clti_s_w_ARG1 %1 = tail call <4 x i32> @llvm.mips.clti.s.w(<4 x i32> %0, i32 14) - store <4 x i32> %1, <4 x i32>* @llvm_mips_clti_s_w_RES + store <4 x i32> %1, <4 x i32>* @llvm_mips_clti_s_w_RES1 + %2 = tail call <4 x i32> @llvm.mips.clti.s.w(<4 x i32> %0, i32 -14) + store <4 x i32> %2, <4 x i32>* @llvm_mips_clti_s_w_RES2 ret void } declare <4 x i32> @llvm.mips.clti.s.w(<4 x i32>, i32) nounwind ; CHECK: llvm_mips_clti_s_w_test: -; CHECK: ld.w -; CHECK: clti_s.w -; CHECK: st.w +; CHECK: ld.w [[RS:\$w[0-9]+]] +; CHECK: clti_s.w [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.w [[RD1]] +; CHECK: clti_s.w [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.w [[RD2]] ; CHECK: .size llvm_mips_clti_s_w_test ; @llvm_mips_clti_s_d_ARG1 = global <2 x i64> , align 16 -@llvm_mips_clti_s_d_RES = global <2 x i64> , align 16 +@llvm_mips_clti_s_d_RES1 = global <2 x i64> , align 16 +@llvm_mips_clti_s_d_RES2 = global <2 x i64> , align 16 define void @llvm_mips_clti_s_d_test() nounwind { entry: %0 = load <2 x i64>, <2 x i64>* @llvm_mips_clti_s_d_ARG1 %1 = tail call <2 x i64> @llvm.mips.clti.s.d(<2 x i64> %0, i32 14) - store <2 x i64> %1, <2 x i64>* @llvm_mips_clti_s_d_RES + store <2 x i64> %1, <2 x i64>* @llvm_mips_clti_s_d_RES1 + %2 = tail call <2 x i64> @llvm.mips.clti.s.d(<2 x i64> %0, i32 -14) + store <2 x i64> %2, <2 x i64>* @llvm_mips_clti_s_d_RES2 ret void } declare <2 x i64> @llvm.mips.clti.s.d(<2 x i64>, i32) nounwind ; CHECK: llvm_mips_clti_s_d_test: -; CHECK: ld.d -; CHECK: clti_s.d -; CHECK: st.d +; CHECK: ld.d [[RS:\$w[0-9]+]] +; CHECK: clti_s.d [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.d [[RD1]] +; CHECK: clti_s.d [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.d [[RD2]] ; CHECK: .size llvm_mips_clti_s_d_test ; @llvm_mips_clti_u_b_ARG1 = global <16 x i8> , align 16 Index: llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll +++ llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll @@ -5,79 +5,99 @@ ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_maxi_s_b_ARG1 = global <16 x i8> , align 16 -@llvm_mips_maxi_s_b_RES = global <16 x i8> , align 16 +@llvm_mips_maxi_s_b_RES1 = global <16 x i8> , align 16 +@llvm_mips_maxi_s_b_RES2 = global <16 x i8> , align 16 define void @llvm_mips_maxi_s_b_test() nounwind { entry: %0 = load <16 x i8>, <16 x i8>* @llvm_mips_maxi_s_b_ARG1 %1 = tail call <16 x i8> @llvm.mips.maxi.s.b(<16 x i8> %0, i32 14) - store <16 x i8> %1, <16 x i8>* @llvm_mips_maxi_s_b_RES + store <16 x i8> %1, <16 x i8>* @llvm_mips_maxi_s_b_RES1 + %2 = tail call <16 x i8> @llvm.mips.maxi.s.b(<16 x i8> %0, i32 -14) + store <16 x i8> %2, <16 x i8>* @llvm_mips_maxi_s_b_RES2 ret void } declare <16 x i8> @llvm.mips.maxi.s.b(<16 x i8>, i32) nounwind ; CHECK: llvm_mips_maxi_s_b_test: -; CHECK: ld.b -; CHECK: maxi_s.b -; CHECK: st.b +; CHECK: ld.b [[RS:\$w[0-9]+]] +; CHECK: maxi_s.b [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.b [[RD1]] +; CHECK: maxi_s.b [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.b [[RD2]] ; CHECK: .size llvm_mips_maxi_s_b_test ; @llvm_mips_maxi_s_h_ARG1 = global <8 x i16> , align 16 -@llvm_mips_maxi_s_h_RES = global <8 x i16> , align 16 +@llvm_mips_maxi_s_h_RES1 = global <8 x i16> , align 16 +@llvm_mips_maxi_s_h_RES2 = global <8 x i16> , align 16 define void @llvm_mips_maxi_s_h_test() nounwind { entry: %0 = load <8 x i16>, <8 x i16>* @llvm_mips_maxi_s_h_ARG1 %1 = tail call <8 x i16> @llvm.mips.maxi.s.h(<8 x i16> %0, i32 14) - store <8 x i16> %1, <8 x i16>* @llvm_mips_maxi_s_h_RES + store <8 x i16> %1, <8 x i16>* @llvm_mips_maxi_s_h_RES1 + %2 = tail call <8 x i16> @llvm.mips.maxi.s.h(<8 x i16> %0, i32 -14) + store <8 x i16> %2, <8 x i16>* @llvm_mips_maxi_s_h_RES2 ret void } declare <8 x i16> @llvm.mips.maxi.s.h(<8 x i16>, i32) nounwind ; CHECK: llvm_mips_maxi_s_h_test: -; CHECK: ld.h -; CHECK: maxi_s.h -; CHECK: st.h +; CHECK: ld.h [[RS:\$w[0-9]+]] +; CHECK: maxi_s.h [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.h [[RD1]] +; CHECK: maxi_s.h [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.h [[RD2]] ; CHECK: .size llvm_mips_maxi_s_h_test ; @llvm_mips_maxi_s_w_ARG1 = global <4 x i32> , align 16 -@llvm_mips_maxi_s_w_RES = global <4 x i32> , align 16 +@llvm_mips_maxi_s_w_RES1 = global <4 x i32> , align 16 +@llvm_mips_maxi_s_w_RES2 = global <4 x i32> , align 16 define void @llvm_mips_maxi_s_w_test() nounwind { entry: %0 = load <4 x i32>, <4 x i32>* @llvm_mips_maxi_s_w_ARG1 %1 = tail call <4 x i32> @llvm.mips.maxi.s.w(<4 x i32> %0, i32 14) - store <4 x i32> %1, <4 x i32>* @llvm_mips_maxi_s_w_RES + store <4 x i32> %1, <4 x i32>* @llvm_mips_maxi_s_w_RES1 + %2 = tail call <4 x i32> @llvm.mips.maxi.s.w(<4 x i32> %0, i32 -14) + store <4 x i32> %2, <4 x i32>* @llvm_mips_maxi_s_w_RES2 ret void } declare <4 x i32> @llvm.mips.maxi.s.w(<4 x i32>, i32) nounwind ; CHECK: llvm_mips_maxi_s_w_test: -; CHECK: ld.w -; CHECK: maxi_s.w -; CHECK: st.w +; CHECK: ld.w [[RS:\$w[0-9]+]] +; CHECK: maxi_s.w [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.w [[RD1]] +; CHECK: maxi_s.w [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.w [[RD2]] ; CHECK: .size llvm_mips_maxi_s_w_test ; @llvm_mips_maxi_s_d_ARG1 = global <2 x i64> , align 16 -@llvm_mips_maxi_s_d_RES = global <2 x i64> , align 16 +@llvm_mips_maxi_s_d_RES1 = global <2 x i64> , align 16 +@llvm_mips_maxi_s_d_RES2 = global <2 x i64> , align 16 define void @llvm_mips_maxi_s_d_test() nounwind { entry: %0 = load <2 x i64>, <2 x i64>* @llvm_mips_maxi_s_d_ARG1 %1 = tail call <2 x i64> @llvm.mips.maxi.s.d(<2 x i64> %0, i32 14) - store <2 x i64> %1, <2 x i64>* @llvm_mips_maxi_s_d_RES + store <2 x i64> %1, <2 x i64>* @llvm_mips_maxi_s_d_RES1 + %2 = tail call <2 x i64> @llvm.mips.maxi.s.d(<2 x i64> %0, i32 -14) + store <2 x i64> %2, <2 x i64>* @llvm_mips_maxi_s_d_RES2 ret void } declare <2 x i64> @llvm.mips.maxi.s.d(<2 x i64>, i32) nounwind ; CHECK: llvm_mips_maxi_s_d_test: -; CHECK: ld.d -; CHECK: maxi_s.d -; CHECK: st.d +; CHECK: ld.d [[RS:\$w[0-9]+]] +; CHECK: maxi_s.d [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.d [[RD1]] +; CHECK: maxi_s.d [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.d [[RD2]] ; CHECK: .size llvm_mips_maxi_s_d_test ; @llvm_mips_maxi_u_b_ARG1 = global <16 x i8> , align 16 @@ -157,79 +177,99 @@ ; CHECK: .size llvm_mips_maxi_u_d_test ; @llvm_mips_mini_s_b_ARG1 = global <16 x i8> , align 16 -@llvm_mips_mini_s_b_RES = global <16 x i8> , align 16 +@llvm_mips_mini_s_b_RES1 = global <16 x i8> , align 16 +@llvm_mips_mini_s_b_RES2 = global <16 x i8> , align 16 define void @llvm_mips_mini_s_b_test() nounwind { entry: %0 = load <16 x i8>, <16 x i8>* @llvm_mips_mini_s_b_ARG1 %1 = tail call <16 x i8> @llvm.mips.mini.s.b(<16 x i8> %0, i32 14) - store <16 x i8> %1, <16 x i8>* @llvm_mips_mini_s_b_RES + store <16 x i8> %1, <16 x i8>* @llvm_mips_mini_s_b_RES1 + %2 = tail call <16 x i8> @llvm.mips.mini.s.b(<16 x i8> %0, i32 -14) + store <16 x i8> %2, <16 x i8>* @llvm_mips_mini_s_b_RES2 ret void } declare <16 x i8> @llvm.mips.mini.s.b(<16 x i8>, i32) nounwind ; CHECK: llvm_mips_mini_s_b_test: -; CHECK: ld.b -; CHECK: mini_s.b -; CHECK: st.b +; CHECK: ld.b [[RS:\$w[0-9]+]] +; CHECK: mini_s.b [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.b [[RD1]] +; CHECK: mini_s.b [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.b [[RD2]] ; CHECK: .size llvm_mips_mini_s_b_test ; @llvm_mips_mini_s_h_ARG1 = global <8 x i16> , align 16 -@llvm_mips_mini_s_h_RES = global <8 x i16> , align 16 +@llvm_mips_mini_s_h_RES1 = global <8 x i16> , align 16 +@llvm_mips_mini_s_h_RES2 = global <8 x i16> , align 16 define void @llvm_mips_mini_s_h_test() nounwind { entry: %0 = load <8 x i16>, <8 x i16>* @llvm_mips_mini_s_h_ARG1 %1 = tail call <8 x i16> @llvm.mips.mini.s.h(<8 x i16> %0, i32 14) - store <8 x i16> %1, <8 x i16>* @llvm_mips_mini_s_h_RES + store <8 x i16> %1, <8 x i16>* @llvm_mips_mini_s_h_RES1 + %2 = tail call <8 x i16> @llvm.mips.mini.s.h(<8 x i16> %0, i32 -14) + store <8 x i16> %2, <8 x i16>* @llvm_mips_mini_s_h_RES2 ret void } declare <8 x i16> @llvm.mips.mini.s.h(<8 x i16>, i32) nounwind ; CHECK: llvm_mips_mini_s_h_test: -; CHECK: ld.h -; CHECK: mini_s.h -; CHECK: st.h +; CHECK: ld.h [[RS:\$w[0-9]+]] +; CHECK: mini_s.h [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.h [[RD1]] +; CHECK: mini_s.h [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.h [[RD2]] ; CHECK: .size llvm_mips_mini_s_h_test ; @llvm_mips_mini_s_w_ARG1 = global <4 x i32> , align 16 -@llvm_mips_mini_s_w_RES = global <4 x i32> , align 16 +@llvm_mips_mini_s_w_RES1 = global <4 x i32> , align 16 +@llvm_mips_mini_s_w_RES2 = global <4 x i32> , align 16 define void @llvm_mips_mini_s_w_test() nounwind { entry: %0 = load <4 x i32>, <4 x i32>* @llvm_mips_mini_s_w_ARG1 %1 = tail call <4 x i32> @llvm.mips.mini.s.w(<4 x i32> %0, i32 14) - store <4 x i32> %1, <4 x i32>* @llvm_mips_mini_s_w_RES + store <4 x i32> %1, <4 x i32>* @llvm_mips_mini_s_w_RES1 + %2 = tail call <4 x i32> @llvm.mips.mini.s.w(<4 x i32> %0, i32 -14) + store <4 x i32> %2, <4 x i32>* @llvm_mips_mini_s_w_RES2 ret void } declare <4 x i32> @llvm.mips.mini.s.w(<4 x i32>, i32) nounwind ; CHECK: llvm_mips_mini_s_w_test: -; CHECK: ld.w -; CHECK: mini_s.w -; CHECK: st.w +; CHECK: ld.w [[RS:\$w[0-9]+]] +; CHECK: mini_s.w [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.w [[RD1]] +; CHECK: mini_s.w [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.w [[RD2]] ; CHECK: .size llvm_mips_mini_s_w_test ; @llvm_mips_mini_s_d_ARG1 = global <2 x i64> , align 16 -@llvm_mips_mini_s_d_RES = global <2 x i64> , align 16 +@llvm_mips_mini_s_d_RES1 = global <2 x i64> , align 16 +@llvm_mips_mini_s_d_RES2 = global <2 x i64> , align 16 define void @llvm_mips_mini_s_d_test() nounwind { entry: %0 = load <2 x i64>, <2 x i64>* @llvm_mips_mini_s_d_ARG1 %1 = tail call <2 x i64> @llvm.mips.mini.s.d(<2 x i64> %0, i32 14) - store <2 x i64> %1, <2 x i64>* @llvm_mips_mini_s_d_RES + store <2 x i64> %1, <2 x i64>* @llvm_mips_mini_s_d_RES1 + %2 = tail call <2 x i64> @llvm.mips.mini.s.d(<2 x i64> %0, i32 -14) + store <2 x i64> %2, <2 x i64>* @llvm_mips_mini_s_d_RES2 ret void } declare <2 x i64> @llvm.mips.mini.s.d(<2 x i64>, i32) nounwind ; CHECK: llvm_mips_mini_s_d_test: -; CHECK: ld.d -; CHECK: mini_s.d -; CHECK: st.d +; CHECK: ld.d [[RS:\$w[0-9]+]] +; CHECK: mini_s.d [[RD1:\$w[0-9]]], [[RS]], 14 +; CHECK: st.d [[RD1]] +; CHECK: mini_s.d [[RD2:\$w[0-9]]], [[RS]], -14 +; CHECK: st.d [[RD2]] ; CHECK: .size llvm_mips_mini_s_d_test ; @llvm_mips_mini_u_b_ARG1 = global <16 x i8> , align 16