Index: llvm/lib/Target/PowerPC/CMakeLists.txt
===================================================================
--- llvm/lib/Target/PowerPC/CMakeLists.txt
+++ llvm/lib/Target/PowerPC/CMakeLists.txt
@@ -48,6 +48,7 @@
   PPCVSXSwapRemoval.cpp
   PPCExpandISEL.cpp
   PPCPreEmitPeephole.cpp
+  PPCLowerMASSVEntries.cpp
   )
 
 add_subdirectory(AsmParser)
Index: llvm/lib/Target/PowerPC/PPC.h
===================================================================
--- llvm/lib/Target/PowerPC/PPC.h
+++ llvm/lib/Target/PowerPC/PPC.h
@@ -29,6 +29,7 @@
   class AsmPrinter;
   class MCInst;
   class MCOperand;
+  class ModulePass;
 
   FunctionPass *createPPCCTRLoops();
 #ifndef NDEBUG
@@ -64,6 +65,10 @@
   void initializePPCMIPeepholePass(PassRegistry&);
   extern char &PPCVSXFMAMutateID;
 
+  ModulePass *createPPCLowerMASSVEntriesPass();
+  void initializePPCLowerMASSVEntriesPass(PassRegistry &);
+  extern char &PPCLowerMASSVEntriesID;
+
   namespace PPCII {
 
   /// Target Operand Flag enum.
Index: llvm/lib/Target/PowerPC/PPCLowerMASSVEntries.cpp
===================================================================
--- /dev/null
+++ llvm/lib/Target/PowerPC/PPCLowerMASSVEntries.cpp
@@ -0,0 +1,163 @@
+//===-- PPCLowerMASSVEntries.cpp ------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements lowering of MASSV (SIMD) entries for specific PowerPC
+// subtargets.
+// Following is an example of a conversion specific to Power9 subtarget:
+// __sind2_massv ---> __sind2_P9
+//
+//===----------------------------------------------------------------------===//
+
+#include "PPC.h"
+#include "PPCSubtarget.h"
+#include "PPCTargetMachine.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/IR/Instructions.h"
+#include "llvm/IR/Module.h"
+
+#define DEBUG_TYPE "ppc-lower-massv-entries"
+
+using namespace llvm;
+
+namespace {
+
+// Length of the suffix "massv", which is specific to IBM MASSV library entries.
+const unsigned MASSVSuffixLength = 5;
+
+static StringRef MASSVFuncs[] = {
+#define TLI_DEFINE_VECFUNC_ARR
+#define TLI_DEFINE_MASSV_VECFUNCS
+#include "llvm/Analysis/VecFuncs.def"
+};
+
+class PPCLowerMASSVEntries : public ModulePass {
+public:
+  static char ID;
+
+  PPCLowerMASSVEntries() : ModulePass(ID) {}
+
+  bool runOnModule(Module &M) override;
+
+  StringRef getPassName() const override { return "PPC Lower MASS Entries"; }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.addRequired<TargetTransformInfoWrapperPass>();
+  }
+
+private:
+  static bool isMASSVFunc(StringRef Name);
+  static StringRef getCPUSuffix(const PPCSubtarget *Subtarget);
+  static std::string createMASSVFuncName(Function &Func,
+                                         const PPCSubtarget *Subtarget);
+  bool lowerMASSVCall(CallInst *CI, Function &Func, Module &M,
+                      const PPCSubtarget *Subtarget);
+};
+
+} // namespace
+
+/// Checks if the specified function name represents an entry in the MASSV
+/// library.
+bool PPCLowerMASSVEntries::isMASSVFunc(StringRef Name) {
+  auto Iter = std::find(std::begin(MASSVFuncs), std::end(MASSVFuncs), Name);
+  return Iter != std::end(MASSVFuncs);
+}
+
+// FIXME:
+/// Returns a string corresponding to the specified PowerPC subtarget. e.g.:
+/// "P8" for Power8, "P9" for Power9. The string is used as a suffix while
+/// generating subtarget-specific MASSV library functions. Current support
+/// includes  Power8 and Power9 subtargets.
+StringRef PPCLowerMASSVEntries::getCPUSuffix(const PPCSubtarget *Subtarget) {
+  // Assume Power8 when Subtarget is unavailable.
+  if (!Subtarget)
+    return "P8";
+  if (Subtarget->hasP9Vector())
+    return "P9";
+  if (Subtarget->hasP8Vector())
+    return "P8";
+
+  report_fatal_error("Unsupported Subtarget: MASSV is supported only on "
+                     "Power8 and Power9 subtargets.");
+}
+
+/// Creates PowerPC subtarget-specific name corresponding to the specified
+/// generic MASSV function, and the PowerPC subtarget.
+std::string
+PPCLowerMASSVEntries::createMASSVFuncName(Function &Func,
+                                          const PPCSubtarget *Subtarget) {
+  StringRef Suffix = getCPUSuffix(Subtarget);
+  auto GenericName = Func.getName().drop_back(MASSVSuffixLength).str();
+  std::string MASSVEntryName = GenericName + Suffix.str();
+  return MASSVEntryName;
+}
+
+/// Lowers generic MASSV entries to PowerPC subtarget-specific MASSV entries.
+/// e.g.: __sind2_massv --> __sind2_P9 for a Power9 subtarget.
+/// Both function prototypes and their callsites are updated during lowering.
+bool PPCLowerMASSVEntries::lowerMASSVCall(CallInst *CI, Function &Func,
+                                          Module &M,
+                                          const PPCSubtarget *Subtarget) {
+  if (CI->use_empty())
+    return false;
+
+  std::string MASSVEntryName = createMASSVFuncName(Func, Subtarget);
+  FunctionCallee FCache = M.getOrInsertFunction(
+      MASSVEntryName, Func.getFunctionType(), Func.getAttributes());
+
+  CallSite CS(CI);
+  IRBuilder<> Builder(CI->getParent(), CI->getIterator());
+  SmallVector<Value *, 4> Args(CS.arg_begin(), CS.arg_end());
+
+  CallInst *NewCI = Builder.CreateCall(FCache, Args);
+  NewCI->setName(CI->getName());
+  CI->replaceAllUsesWith(NewCI);
+
+  return true;
+}
+
+bool PPCLowerMASSVEntries::runOnModule(Module &M) {
+  bool Changed = false;
+
+  auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
+  if (!TPC)
+    return Changed;
+
+  auto &TM = TPC->getTM<PPCTargetMachine>();
+  const PPCSubtarget *Subtarget;
+
+  for (Function &Func : M) {
+    if (!Func.isDeclaration())
+      continue;
+
+    if (!isMASSVFunc(Func.getName()))
+      continue;
+
+    for (auto *User : Func.users()) {
+      auto *CI = dyn_cast<CallInst>(User);
+      if (!CI)
+        continue;
+
+      Subtarget = &TM.getSubtarget<PPCSubtarget>(*CI->getParent()->getParent());
+      Changed |= lowerMASSVCall(CI, Func, M, Subtarget);
+    }
+  }
+
+  return Changed;
+}
+
+char PPCLowerMASSVEntries::ID = 0;
+
+char &llvm::PPCLowerMASSVEntriesID = PPCLowerMASSVEntries::ID;
+
+INITIALIZE_PASS(PPCLowerMASSVEntries, DEBUG_TYPE, "Lower MASSV entries", false,
+                false)
+
+ModulePass *llvm::createPPCLowerMASSVEntriesPass() {
+  return new PPCLowerMASSVEntries();
+}
Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -105,6 +105,7 @@
   initializePPCPreEmitPeepholePass(PR);
   initializePPCTLSDynamicCallPass(PR);
   initializePPCMIPeepholePass(PR);
+  initializePPCLowerMASSVEntriesPass(PR);
 }
 
 /// Return the datalayout string of a subtarget.
@@ -375,6 +376,9 @@
     addPass(createPPCBoolRetToIntPass());
   addPass(createAtomicExpandPass());
 
+  // Lower generic MASSV routines to PowerPC subtarget-specific entries.
+  addPass(createPPCLowerMASSVEntriesPass());
+
   // For the BG/Q (or if explicitly requested), add explicit data prefetch
   // intrinsics.
   bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
Index: llvm/test/CodeGen/PowerPC/lower-massv.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/lower-massv.ll
@@ -0,0 +1,585 @@
+; RUN: llc -mcpu=pwr9 < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefix CHECK-PWR9 -check-prefix CHECK-ALL %s 
+; RUN: llc -mcpu=pwr8 < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefix CHECK-PWR8 -check-prefix CHECK-ALL %s 
+; RUN: llc -mcpu=pwr8 < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefix CHECK-DFLT -check-prefix CHECK-ALL %s 
+
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+declare <2 x double> @__cbrtd2_massv(<2 x double>)
+declare <4 x float> @__cbrtf4_massv(<4 x float>)
+
+declare <2 x double> @__powd2_massv(<2 x double>, <2 x double>)
+declare <4 x float> @__powf4_massv(<4 x float>, <4 x float>)
+
+declare <2 x double> @__sqrtd2_massv(<2 x double>)
+declare <4 x float> @__sqrtf4_massv(<4 x float>)
+
+declare <2 x double> @__expd2_massv(<2 x double>)
+declare <4 x float> @__expf4_massv(<4 x float>)
+
+declare <2 x double> @__exp2d2_massv(<2 x double>)
+declare <4 x float> @__exp2f4_massv(<4 x float>)
+
+declare <2 x double> @__expm1d2_massv(<2 x double>)
+declare <4 x float> @__expm1f4_massv(<4 x float>)
+
+declare <2 x double> @__logd2_massv(<2 x double>)
+declare <4 x float> @__logf4_massv(<4 x float>)
+
+declare <2 x double> @__log1pd2_massv(<2 x double>)
+declare <4 x float> @__log1pf4_massv(<4 x float>)
+
+declare <2 x double> @__log10d2_massv(<2 x double>)
+declare <4 x float> @__log10f4_massv(<4 x float>)
+
+declare <2 x double> @__log2d2_massv(<2 x double>)
+declare <4 x float> @__log2f4_massv(<4 x float>)
+
+declare <2 x double> @__sind2_massv(<2 x double>)
+declare <4 x float> @__sinf4_massv(<4 x float>)
+
+declare <2 x double> @__cosd2_massv(<2 x double>)
+declare <4 x float> @__cosf4_massv(<4 x float>)
+
+declare <2 x double> @__tand2_massv(<2 x double>)
+declare <4 x float> @__tanf4_massv(<4 x float>)
+
+declare <2 x double> @__asind2_massv(<2 x double>)
+declare <4 x float> @__asinf4_massv(<4 x float>)
+
+declare <2 x double> @__acosd2_massv(<2 x double>)
+declare <4 x float> @__acosf4_massv(<4 x float>)
+
+declare <2 x double> @__atand2_massv(<2 x double>)
+declare <4 x float> @__atanf4_massv(<4 x float>)
+
+declare <2 x double> @__atan2d2_massv(<2 x double>)
+declare <4 x float> @__atan2f4_massv(<4 x float>)
+
+declare <2 x double> @__sinhd2_massv(<2 x double>)
+declare <4 x float> @__sinhf4_massv(<4 x float>)
+
+declare <2 x double> @__coshd2_massv(<2 x double>)
+declare <4 x float> @__coshf4_massv(<4 x float>)
+
+declare <2 x double> @__tanhd2_massv(<2 x double>)
+declare <4 x float> @__tanhf4_massv(<4 x float>)
+
+declare <2 x double> @__asinhd2_massv(<2 x double>)
+declare <4 x float> @__asinhf4_massv(<4 x float>)
+
+declare <2 x double> @__acoshd2_massv(<2 x double>)
+declare <4 x float> @__acoshf4_massv(<4 x float>)
+
+declare <2 x double> @__atanhd2_massv(<2 x double>)
+declare <4 x float> @__atanhf4_massv(<4 x float>)
+
+; cbrt without the power9-vector attribute on the caller
+; check massv calls are correctly targeted for Power8
+define <2 x double>  @cbrt_f64_massv_nopwr9(<2 x double> %opnd) #0 {
+; CHECK-ALL-LABEL: @cbrt_f64_massv_nopwr9
+; CHECK-DFLT: bl __cbrtd2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__cbrtd2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+; cbrt with the power9-vector attribute on the caller
+; check massv calls are correctly targeted for Power9
+define <2 x double>  @cbrt_f64_massv_pwr9(<2 x double> %opnd) #1 {
+; CHECK-ALL-LABEL: @cbrt_f64_massv_pwr9
+; CHECK-DFLT: bl __cbrtd2_P9
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__cbrtd2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+; following tests check generation of subtarget-specific calls
+; cbrt
+define <2 x double>  @cbrt_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @cbrt_f64_massv
+; CHECK-PWR9: bl __cbrtd2_P9
+; CHECK-PWR8: bl __cbrtd2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__cbrtd2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @cbrt_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @cbrt_f32_massv
+; CHECK-PWR9: bl __cbrtf4_P9
+; CHECK-PWR8: bl __cbrtf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__cbrtf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; pow
+define <2 x double>  @pow_f64_massv(<2 x double> %opnd1, <2 x double> %opnd2) {
+; CHECK-ALL-LABEL: @pow_f64_massv
+; CHECK-PWR9: bl __powd2_P9
+; CHECK-PWR8: bl __powd2_P8
+; CHECK-ALL: blr
+;
+ %1 = call <2 x double> @__powd2_massv(<2 x double> %opnd1, <2 x double> %opnd2)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @pow_f32_massv(<4 x float> %opnd1, <4 x float> %opnd2) {
+; CHECK-ALL-LABEL: @pow_f32_massv
+; CHECK-PWR9: bl __powf4_P9
+; CHECK-PWR8: bl __powf4_P8
+; CHECK-ALL: blr
+;
+ %1 = call <4 x float> @__powf4_massv(<4 x float> %opnd1, <4 x float> %opnd2)
+  ret <4 x float> %1 
+}
+
+; sqrt
+define <2 x double>  @sqrt_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @sqrt_f64_massv
+; CHECK-PWR9: bl __sqrtd2_P9
+; CHECK-PWR8: bl __sqrtd2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__sqrtd2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @sqrt_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @sqrt_f32_massv
+; CHECK-PWR9: bl __sqrtf4_P9
+; CHECK-PWR8: bl __sqrtf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__sqrtf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; exp
+define <2 x double>  @exp_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @exp_f64_massv
+; CHECK-PWR9: bl __expd2_P9
+; CHECK-PWR8: bl __expd2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__expd2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @exp_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @exp_f32_massv
+; CHECK-PWR9: bl __expf4_P9
+; CHECK-PWR8: bl __expf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__expf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; exp2
+define <2 x double>  @exp2_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @exp2_f64_massv
+; CHECK-PWR9: bl __exp2d2_P9
+; CHECK-PWR8: bl __exp2d2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__exp2d2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @exp2_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @exp2_f32_massv
+; CHECK-PWR9: bl __exp2f4_P9
+; CHECK-PWR8: bl __exp2f4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__exp2f4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; expm1
+define <2 x double>  @expm1_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @expm1_f64_massv
+; CHECK-PWR9: bl __expm1d2_P9
+; CHECK-PWR8: bl __expm1d2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__expm1d2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @expm1_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @expm1_f32_massv
+; CHECK-PWR9: bl __expm1f4_P9
+; CHECK-PWR8: bl __expm1f4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__expm1f4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; log
+define <2 x double>  @log_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @log_f64_massv
+; CHECK-PWR9: bl __logd2_P9
+; CHECK-PWR8: bl __logd2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__logd2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @log_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @log_f32_massv
+; CHECK-PWR9: bl __logf4_P9
+; CHECK-PWR8: bl __logf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__logf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; log1p
+define <2 x double>  @log1p_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @log1p_f64_massv
+; CHECK-PWR9: bl __log1pd2_P9
+; CHECK-PWR8: bl __log1pd2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__log1pd2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @log1p_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @log1p_f32_massv
+; CHECK-PWR9: bl __log1pf4_P9
+; CHECK-PWR8: bl __log1pf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__log1pf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; log10
+define <2 x double>  @log10_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @log10_f64_massv
+; CHECK-PWR9: bl __log10d2_P9
+; CHECK-PWR8: bl __log10d2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__log10d2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @log10_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @log10_f32_massv
+; CHECK-PWR9: bl __log10f4_P9
+; CHECK-PWR8: bl __log10f4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__log10f4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; log2
+define <2 x double>  @log2_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @log2_f64_massv
+; CHECK-PWR9: bl __log2d2_P9
+; CHECK-PWR8: bl __log2d2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__log2d2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @log2_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @log2_f32_massv
+; CHECK-PWR9: bl __log2f4_P9
+; CHECK-PWR8: bl __log2f4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__log2f4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; sin
+define <2 x double>  @sin_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @sin_f64_massv
+; CHECK-PWR9: bl __sind2_P9
+; CHECK-PWR8: bl __sind2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__sind2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @sin_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @sin_f32_massv
+; CHECK-PWR9: bl __sinf4_P9
+; CHECK-PWR8: bl __sinf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__sinf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; cos
+define <2 x double>  @cos_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @cos_f64_massv
+; CHECK-PWR9: bl __cosd2_P9
+; CHECK-PWR8: bl __cosd2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__cosd2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @cos_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @cos_f32_massv
+; CHECK-PWR9: bl __cosf4_P9
+; CHECK-PWR8: bl __cosf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__cosf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; tan
+define <2 x double>  @tan_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @tan_f64_massv
+; CHECK-PWR9: bl __tand2_P9
+; CHECK-PWR8: bl __tand2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__tand2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @tan_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @tan_f32_massv
+; CHECK-PWR9: bl __tanf4_P9
+; CHECK-PWR8: bl __tanf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__tanf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; asin
+define <2 x double>  @asin_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @asin_f64_massv
+; CHECK-PWR9: bl __asind2_P9
+; CHECK-PWR8: bl __asind2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__asind2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @asin_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @asin_f32_massv
+; CHECK-PWR9: bl __asinf4_P9
+; CHECK-PWR8: bl __asinf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__asinf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; acos
+define <2 x double>  @acos_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @acos_f64_massv
+; CHECK-PWR9: bl __acosd2_P9
+; CHECK-PWR8: bl __acosd2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__acosd2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @acos_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @acos_f32_massv
+; CHECK-PWR9: bl __acosf4_P9
+; CHECK-PWR8: bl __acosf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__acosf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; atan
+define <2 x double>  @atan_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @atan_f64_massv
+; CHECK-PWR9: bl __atand2_P9
+; CHECK-PWR8: bl __atand2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__atand2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @atan_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @atan_f32_massv
+; CHECK-PWR9: bl __atanf4_P9
+; CHECK-PWR8: bl __atanf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__atanf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; atan2
+define <2 x double>  @atan2_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @atan2_f64_massv
+; CHECK-PWR9: bl __atan2d2_P9
+; CHECK-PWR8: bl __atan2d2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__atan2d2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @atan2_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @atan2_f32_massv
+; CHECK-PWR9: bl __atan2f4_P9
+; CHECK-PWR8: bl __atan2f4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__atan2f4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; sinh
+define <2 x double>  @sinh_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @sinh_f64_massv
+; CHECK-PWR9: bl __sinhd2_P9
+; CHECK-PWR8: bl __sinhd2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__sinhd2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @sinh_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @sinh_f32_massv
+; CHECK-PWR9: bl __sinhf4_P9
+; CHECK-PWR8: bl __sinhf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__sinhf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; cosh
+define <2 x double>  @cosh_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @cosh_f64_massv
+; CHECK-PWR9: bl __coshd2_P9
+; CHECK-PWR8: bl __coshd2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__coshd2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @cosh_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @cosh_f32_massv
+; CHECK-PWR9: bl __coshf4_P9
+; CHECK-PWR8: bl __coshf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__coshf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; tanh
+define <2 x double>  @tanh_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @tanh_f64_massv
+; CHECK-PWR9: bl __tanhd2_P9
+; CHECK-PWR8: bl __tanhd2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__tanhd2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @tanh_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @tanh_f32_massv
+; CHECK-PWR9: bl __tanhf4_P9
+; CHECK-PWR8: bl __tanhf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__tanhf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; asinh
+define <2 x double>  @asinh_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @asinh_f64_massv
+; CHECK-PWR9: bl __asinhd2_P9
+; CHECK-PWR8: bl __asinhd2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__asinhd2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @asinh_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @asinh_f32_massv
+; CHECK-PWR9: bl __asinhf4_P9
+; CHECK-PWR8: bl __asinhf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__asinhf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; acosh
+define <2 x double>  @acosh_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @acosh_f64_massv
+; CHECK-PWR9: bl __acoshd2_P9
+; CHECK-PWR8: bl __acoshd2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__acoshd2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @acosh_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @acosh_f32_massv
+; CHECK-PWR9: bl __acoshf4_P9
+; CHECK-PWR8: bl __acoshf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__acoshf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+; atanh
+define <2 x double>  @atanh_f64_massv(<2 x double> %opnd) {
+; CHECK-ALL-LABEL: @atanh_f64_massv
+; CHECK-PWR9: bl __atanhd2_P9
+; CHECK-PWR8: bl __atanhd2_P8
+; CHECK-ALL: blr
+;
+  %1 = call <2 x double> @__atanhd2_massv(<2 x double> %opnd)
+  ret <2 x double> %1 
+}
+
+define <4 x float>  @atanh_f32_massv(<4 x float> %opnd) {
+; CHECK-ALL-LABEL: @atanh_f32_massv
+; CHECK-PWR9: bl __atanhf4_P9
+; CHECK-PWR8: bl __atanhf4_P8
+; CHECK-ALL: blr
+;
+  %1 = call <4 x float> @__atanhf4_massv(<4 x float> %opnd)
+  ret <4 x float> %1 
+}
+
+attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+attributes #1 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,+power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
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