AMDGPU: Remove unnecessary check for isFullCopy

[arsenm]

Summary

Subregister indexes are not used for physical register operands, so
isFullCopy is implied by the physical register check.

[rampitec]

LGTM

[arsenm]

r356956

[hakzsam]

Hi Matt,

This change introduces a regression with Overwatch and RADV (cf. https://bugs.freedesktop.org/show_bug.cgi?id=110476).

Here's the attached LLVM IR https://pastebin.com/raw/VqRF4unW

Can you have a look?
Thanks!

[arsenm]

In D59772#1473800, @hakzsam wrote:

Hi Matt,

This change introduces a regression with Overwatch and RADV (cf. https://bugs.freedesktop.org/show_bug.cgi?id=110476).

Here's the attached LLVM IR https://pastebin.com/raw/VqRF4unW

Can you have a look?
Thanks!

r358890

[hakzsam]

In D59772#1474229, @arsenm wrote:

In D59772#1473800, @hakzsam wrote:

Hi Matt,

This change introduces a regression with Overwatch and RADV (cf. https://bugs.freedesktop.org/show_bug.cgi?id=110476).

Here's the attached LLVM IR https://pastebin.com/raw/VqRF4unW

Can you have a look?
Thanks!

r358890

I confirm it's fixed, thanks a lot!

lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

 }
 
 static bool isEndCF(const MachineInstr& MI, const SIRegisterInfo* TRI) {
   return MI.getOpcode() == AMDGPU::S_OR_B64 &&
          MI.modifiesRegister(AMDGPU::EXEC, TRI);
 }
 
 static bool isFullExecCopy(const MachineInstr& MI) {
-  return MI.isFullCopy() && MI.getOperand(1).getReg() == AMDGPU::EXEC;
+  return MI.getOperand(1).getReg() == AMDGPU::EXEC;
 }
 
 static unsigned getOrNonExecReg(const MachineInstr &MI,
                                 const SIInstrInfo &TII) {
   auto Op = TII.getNamedOperand(MI, AMDGPU::OpName::src1);
   if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)
      return Op->getReg();
   Op = TII.getNamedOperand(MI, AMDGPU::OpName::src0);