AMDGPU: Set hasSideEffects 0 on _term instructions

[arsenm]

Summary

These were defaulting to true, but they are just wrappers around bit
operations. This avoids regressions in the exec mask optimization
passes in a future commit.

[rampitec]

LGTM

[rampitec]

One question though, did it pass precheckin? Make sure it did before submission.

[arsenm]

r356952

lib/Target/AMDGPU/SIInstructions.td

 def GET_GROUPSTATICSIZE : SPseudoInstSI <(outs SReg_32:$sdst), (ins),
   [(set SReg_32:$sdst, (int_amdgcn_groupstaticsize))]>;
 } // End let usesCustomInserter = 1, SALU = 1
 
 def S_MOV_B64_term : SPseudoInstSI<(outs SReg_64:$dst),
    (ins SSrc_b64:$src0)> {
   let isAsCheapAsAMove = 1;
   let isTerminator = 1;
+  let hasSideEffects = 0;
 }
 
 def S_XOR_B64_term : SPseudoInstSI<(outs SReg_64:$dst),
    (ins SSrc_b64:$src0, SSrc_b64:$src1)> {
   let isAsCheapAsAMove = 1;
   let isTerminator = 1;
+  let hasSideEffects = 0;
   let Defs = [SCC];
 }
 
 def S_ANDN2_B64_term : SPseudoInstSI<(outs SReg_64:$dst),
    (ins SSrc_b64:$src0, SSrc_b64:$src1)> {
   let isAsCheapAsAMove = 1;
   let isTerminator = 1;
+  let hasSideEffects = 0;
 }
 
 def WAVE_BARRIER : SPseudoInstSI<(outs), (ins),
   [(int_amdgcn_wave_barrier)]> {
   let SchedRW = [];
   let hasNoSchedulingInfo = 1;
   let hasSideEffects = 1;
   let mayLoad = 1;