Index: lib/Target/Mips/MipsInstrFPU.td
===================================================================
--- lib/Target/Mips/MipsInstrFPU.td
+++ lib/Target/Mips/MipsInstrFPU.td
@@ -242,6 +242,18 @@
   let AddedComplexity = 20;
 }
 
+class BC0F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
+             bit DelaySlot = 1> :
+  InstSE<(outs), (ins opnd:$offset),
+         !strconcat(opstr, "\t$offset"),
+         [], Itin,
+         FrmFI, opstr> {
+  let isBranch = 1;
+  let isTerminator = 1;
+  let hasDelaySlot = DelaySlot;
+  let Defs = [AT];
+}
+
 class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
               SDPatternOperator Op = null_frag, bit DelaySlot = 1> :
   InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
@@ -560,6 +572,10 @@
 def MIPS_BRANCH_F  : PatLeaf<(i32 0)>;
 def MIPS_BRANCH_T  : PatLeaf<(i32 1)>;
 
+def BC0F : MMRel, BC0F_FT<"bc0f", brtarget, IIBranch>,
+           BC0F_FM<0, 0>, ISA_MIPS1_ONLY;
+def BC0T : MMRel, BC0F_FT<"bc0t", brtarget, IIBranch>,
+           BC0F_FM<0, 1>, ISA_MIPS1_ONLY;
 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>,
            BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
 def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, IIBranch, MIPS_BRANCH_F, 0>,
Index: lib/Target/Mips/MipsInstrFormats.td
===================================================================
--- lib/Target/Mips/MipsInstrFormats.td
+++ lib/Target/Mips/MipsInstrFormats.td
@@ -750,6 +750,20 @@
   let Inst{5-0}   = funct;
 }
 
+class BC0F_FM<bit HasDelaySlot, bit tf> : StdArch {
+  bits<3>  fcc;
+  bits<16> offset;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0x10;
+  let Inst{25-21} = 0x8;
+  let Inst{20-18} = 0x0;
+  let Inst{17} = HasDelaySlot;
+  let Inst{16} = tf;
+  let Inst{15-0} = offset;
+}
+
 class BC1F_FM<bit nd, bit tf> : StdArch {
   bits<3>  fcc;
   bits<16> offset;
Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -148,6 +148,8 @@
 //===----------------------------------------------------------------------===//
 def HasMips2     :    Predicate<"Subtarget->hasMips2()">,
                       AssemblerPredicate<"FeatureMips2">;
+def NotMips2     :    Predicate<"!Subtarget->hasMips2()">,
+                      AssemblerPredicate<"!FeatureMips2">;
 def HasMips3_32  :    Predicate<"Subtarget->hasMips3_32()">,
                       AssemblerPredicate<"FeatureMips3_32">;
 def HasMips3_32r2 :   Predicate<"Subtarget->hasMips3_32r2()">,
@@ -223,6 +225,9 @@
 class ISA_MIPS1_NOT_32R6_64R6 {
   list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
 }
+class ISA_MIPS1_ONLY {
+  list<Predicate> InsnPredicates = [NotMips2];
+}
 class ISA_MIPS2    { list<Predicate> InsnPredicates = [HasMips2]; }
 class ISA_MIPS2_NOT_32R6_64R6 {
   list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
Index: test/MC/Disassembler/Mips/mips1.txt
===================================================================
--- /dev/null
+++ test/MC/Disassembler/Mips/mips1.txt
@@ -0,0 +1,8 @@
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips1 | FileCheck %s
+
+# CHECK: bc0f 1332
+0x41 0x00 0x01 0x4d
+
+# CHECK: bc0t 1332
+0x41 0x01 0x01 0x4d
+
Index: test/MC/Mips/mips1/valid.s
===================================================================
--- test/MC/Mips/mips1/valid.s
+++ test/MC/Mips/mips1/valid.s
@@ -16,6 +16,8 @@
         addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         and       $s7,$v0,$12
         and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc0f      4                    # CHECK: bc0f 4        # encoding: [0x41,0x00,0x00,0x01]
+        bc0t      4                    # CHECK: bc0t 4        # encoding: [0x41,0x01,0x00,0x01]
         bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1t      $fcc0, 4             # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
Index: test/MC/Mips/mips2/invalid-mips1.s
===================================================================
--- /dev/null
+++ test/MC/Mips/mips2/invalid-mips1.s
@@ -0,0 +1,10 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \
+# RUN:     2>%t1
+# RUN: FileCheck %s < %t1
+
+        .set noat
+        bc0f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc0t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+
Index: test/MC/Mips/mips32/invalid-mips1.s
===================================================================
--- /dev/null
+++ test/MC/Mips/mips32/invalid-mips1.s
@@ -0,0 +1,10 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 \
+# RUN:     2>%t1
+# RUN: FileCheck %s < %t1
+
+        .set noat
+        bc0f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc0t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+