Index: lib/Target/Mips/MipsInstrFormats.td
===================================================================
--- lib/Target/Mips/MipsInstrFormats.td
+++ lib/Target/Mips/MipsInstrFormats.td
@@ -815,6 +815,19 @@
   let Inst{5-0}   = funct;
 }
 
+class BC0F_FM<bit IsLikely, bit tf> : StdArch {
+  bits<16> offset;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0x10;
+  let Inst{25-21} = 0x8;
+  let Inst{20-18} = 0x0;
+  let Inst{17} = IsLikely;
+  let Inst{16} = tf;
+  let Inst{15-0} = offset;
+}
+
 class BC1F_FM<bit nd, bit tf> : StdArch {
   bits<3>  fcc;
   bits<16> offset;
Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -1225,6 +1225,19 @@
   let TwoOperandAliasConstraint = "$rs = $rt";
 }
 
+// COP0 branch instructions
+class BC0F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
+             bit DelaySlot = 1> :
+  InstSE<(outs), (ins opnd:$offset),
+         !strconcat(opstr, "\t$offset"),
+         [], Itin,
+         FrmFI, opstr> {
+  let isBranch = 1;
+  let isTerminator = 1;
+  let hasDelaySlot = DelaySlot;
+  let Defs = [AT];
+}
+
 // Arithmetic Multiply ADD/SUB
 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
   InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
@@ -1988,6 +2001,14 @@
               BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
 def B       : UncondBranch<BEQ>;
 
+let AdditionalPredicates = [NotInMicroMips, NotCnMips] in {
+  def BC0F : MMRel, BC0F_FT<"bc0f", brtarget, II_BC0F>,
+             BC0F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
+  def BC0T : MMRel, BC0F_FT<"bc0t", brtarget, II_BC0T>,
+             BC0F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
+}
+
+
 def JAL  : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
 let AdditionalPredicates = [NotInMicroMips] in {
   def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
Index: lib/Target/Mips/MipsSchedule.td
===================================================================
--- lib/Target/Mips/MipsSchedule.td
+++ lib/Target/Mips/MipsSchedule.td
@@ -39,6 +39,8 @@
 def II_BBIT             : InstrItinClass; // bbit[01], bbit[01]32
 def II_BALC             : InstrItinClass;
 def II_BC               : InstrItinClass;
+def II_BC0F             : InstrItinClass;
+def II_BC0T             : InstrItinClass;
 def II_BC1F             : InstrItinClass;
 def II_BC1FL            : InstrItinClass;
 def II_BC1T             : InstrItinClass;
@@ -473,6 +475,8 @@
   InstrItinData<II_BALC            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_BBIT            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_BC              , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_BC0F            , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_BC0T            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_BC1F            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_BC1FL           , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_BC1T            , [InstrStage<1,  [ALU]>]>,
Index: lib/Target/Mips/MipsScheduleGeneric.td
===================================================================
--- lib/Target/Mips/MipsScheduleGeneric.td
+++ lib/Target/Mips/MipsScheduleGeneric.td
@@ -391,8 +391,8 @@
 // ---------------------------------
 //
 // c.<cc>.[ds], bc1[tf], bc1[tf]l
-def : ItinRW<[GenericWriteFPUCmp], [II_C_CC_D, II_C_CC_S, II_BC1F, II_BC1T,
-                                    II_BC1FL, II_BC1TL]>;
+def : ItinRW<[GenericWriteFPUCmp], [II_C_CC_D, II_C_CC_S, II_BC0F, II_BC0T,
+                                    II_BC1F, II_BC1T, II_BC1FL, II_BC1TL]>;
 
 def : ItinRW<[GenericWriteFPUCmp], [II_CMP_CC_D, II_CMP_CC_S]>;
 
Index: lib/Target/Mips/MipsScheduleP5600.td
===================================================================
--- lib/Target/Mips/MipsScheduleP5600.td
+++ lib/Target/Mips/MipsScheduleP5600.td
@@ -544,7 +544,8 @@
 
 // bc1[ft], cfc1, mfc1, mfhc1, movf, movt
 def : ItinRW<[P5600WriteMoveFPUToGPR],
-             [II_BC1F, II_BC1FL, II_BC1T, II_BC1TL, II_CFC1, II_MFC1, II_MFHC1, II_MOVF, II_MOVT]>;
+             [II_BC0F, II_BC0T, II_BC1F, II_BC1FL, II_BC1T, II_BC1TL, II_CFC1,
+              II_MFC1, II_MFHC1, II_MOVF, II_MOVT]>;
 
 // swc1, swxc1, st.[bhwd]
 def : ItinRW<[P5600WriteStoreFPUS], [II_SDC1, II_SDXC1, II_SUXC1, II_SWC1,
Index: test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
+++ test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
@@ -12,6 +12,8 @@
 0x21 0x48 0x86 0x00 # CHECK: addu $9, $4, $6
 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
 0x24 0xb8 0x4c 0x00 # CHECK: and $23, $2, $12
+0x4d 0x01 0x00 0x41 # CHECK: bc0f 1336
+0x4d 0x01 0x01 0x41 # CHECK: bc0t 1336
 0x01 0x00 0x00 0x45 # CHECK: bc1f 8
 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
 0x01 0x00 0x01 0x45 # CHECK: bc1t 8
Index: test/MC/Disassembler/Mips/mips1/valid-mips1.txt
===================================================================
--- test/MC/Disassembler/Mips/mips1/valid-mips1.txt
+++ test/MC/Disassembler/Mips/mips1/valid-mips1.txt
@@ -70,6 +70,8 @@
 0x44 0x51 0xa8 0x00 # CHECK: cfc1 $17, $21
 0x44 0x9e 0x48 0x00 # CHECK: mtc1 $fp, $f9
 0x44 0xc6 0xd0 0x00 # CHECK: ctc1 $6, $26
+0x41 0x00 0x01 0x4d # CHECK: bc0f 1336
+0x41 0x01 0x01 0x4d # CHECK: bc0t 1336
 0x45 0x00 0x00 0x01 # CHECK: bc1f 8
 0x45 0x01 0x00 0x01 # CHECK: bc1t 8
 0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15
Index: test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
+++ test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
@@ -13,6 +13,8 @@
 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
 0x24 0xb8 0x4c 0x00 # CHECK: and $23, $2, $12
 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
+0x4d 0x01 0x00 0x41 # CHECK: bc0f 1336
+0x4d 0x01 0x01 0x41 # CHECK: bc0t 1336
 0x01 0x00 0x00 0x45 # CHECK: bc1f 8
 0x0c 0x00 0x02 0x45 # CHECK: bc1fl 52
 0x01 0x00 0x01 0x45 # CHECK: bc1t 8
Index: test/MC/Disassembler/Mips/mips2/valid-mips2.txt
===================================================================
--- test/MC/Disassembler/Mips/mips2/valid-mips2.txt
+++ test/MC/Disassembler/Mips/mips2/valid-mips2.txt
@@ -108,6 +108,8 @@
 0x44 0x51 0xa8 0x00 # CHECK: cfc1 $17, $21
 0x44 0x9e 0x48 0x00 # CHECK: mtc1 $fp, $f9
 0x44 0xc6 0xd0 0x00 # CHECK: ctc1 $6, $26
+0x41 0x00 0x01 0x4d # CHECK: bc0f 1336
+0x41 0x01 0x01 0x4d # CHECK: bc0t 1336
 0x45 0x00 0x00 0x01 # CHECK: bc1f 8
 0x45 0x01 0x00 0x01 # CHECK: bc1t 8
 0x45 0x02 0x00 0x0c # CHECK: bc1fl 52
Index: test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
+++ test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
@@ -13,6 +13,8 @@
 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
 0x24 0xb8 0x4c 0x00 # CHECK: and $23, $2, $12
 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
+0x4d 0x01 0x00 0x41 # CHECK: bc0f 1336
+0x4d 0x01 0x01 0x41 # CHECK: bc0t 1336
 0x01 0x00 0x00 0x45 # CHECK: bc1f 8
 0x0c 0x00 0x02 0x45 # CHECK: bc1fl 52
 0x01 0x00 0x01 0x45 # CHECK: bc1t 8
Index: test/MC/Disassembler/Mips/mips3/valid-mips3.txt
===================================================================
--- test/MC/Disassembler/Mips/mips3/valid-mips3.txt
+++ test/MC/Disassembler/Mips/mips3/valid-mips3.txt
@@ -132,6 +132,8 @@
 0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4
 0x3a 0x00 0x27 0x12 # CHECK: xori $zero, $16, 10002       
 0x3c 0x00 0x00 0x80 # CHECK: lui $zero, 128
+0x41 0x00 0x01 0x4d # CHECK: bc0f 1336
+0x41 0x01 0x01 0x4d # CHECK: bc0t 1336
 0x42 0x00 0x00 0x01 # CHECK: tlbr
 0x42 0x00 0x00 0x02 # CHECK: tlbwi
 0x42 0x00 0x00 0x06 # CHECK: tlbwr
Index: test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
+++ test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
@@ -12,6 +12,8 @@
 0x25 0xf0 0x80 0x00 # CHECK: move $fp, $4
 0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
 0x4c 0x01 0x00 0x10 # CHECK: b 1332
+0x4d 0x01 0x00 0x41 # CHECK: bc0f 1336
+0x4d 0x01 0x01 0x41 # CHECK: bc0t 1336
 0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
Index: test/MC/Disassembler/Mips/mips32/valid-mips32.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32/valid-mips32.txt
+++ test/MC/Disassembler/Mips/mips32/valid-mips32.txt
@@ -150,6 +150,8 @@
 0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x40 0x08 0x80 0x04 # CHECK: mfc0 $8, $16, 4
 0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
+0x41 0x00 0x01 0x4d # CHECK: bc0f 1336
+0x41 0x01 0x01 0x4d # CHECK: bc0t 1336
 0x42 0x00 0x00 0x01 # CHECK: tlbr
 0x42 0x00 0x00 0x02 # CHECK: tlbwi
 0x42 0x00 0x00 0x06 # CHECK: tlbwr
Index: test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
+++ test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
@@ -13,6 +13,8 @@
 0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
 0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
 0x4c 0x01 0x00 0x10 # CHECK: b 1332
+0x4d 0x01 0x00 0x41 # CHECK: bc0f 1336
+0x4d 0x01 0x01 0x41 # CHECK: bc0t 1336
 0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
Index: test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
+++ test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
@@ -156,6 +156,8 @@
 0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x40 0x08 0x80 0x04 # CHECK: mfc0 $8, $16, 4
 0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
+0x41 0x00 0x01 0x4d # CHECK: bc0f 1336
+0x41 0x01 0x01 0x4d # CHECK: bc0t 1336
 0x41 0x60 0x60 0x00 # CHECK: di
 0x41 0x60 0x60 0x20 # CHECK: ei
 0x41 0x6e 0x60 0x20 # CHECK: ei $14
Index: test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
+++ test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
@@ -10,6 +10,8 @@
 0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
 0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
 0x4c 0x01 0x00 0x10 # CHECK: b 1332
+0x4d 0x01 0x00 0x41 # CHECK: bc0f 1336
+0x4d 0x01 0x01 0x41 # CHECK: bc0t 1336
 0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
Index: test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
+++ test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
@@ -153,6 +153,8 @@
 0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x40 0x08 0x80 0x04 # CHECK: mfc0 $8, $16, 4
 0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
+0x41 0x00 0x01 0x4d # CHECK: bc0f 1336
+0x41 0x01 0x01 0x4d # CHECK: bc0t 1336
 0x41 0x60 0x60 0x00 # CHECK: di
 0x41 0x60 0x60 0x20 # CHECK: ei
 0x41 0x6e 0x60 0x20 # CHECK: ei $14
Index: test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
+++ test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
@@ -10,6 +10,8 @@
 0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
 0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
 0x4c 0x01 0x00 0x10 # CHECK: b 1332
+0x4d 0x01 0x00 0x41 # CHECK: bc0f 1336
+0x4d 0x01 0x01 0x41 # CHECK: bc0t 1336
 0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
Index: test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
+++ test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
@@ -153,6 +153,8 @@
 0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x40 0x08 0x80 0x04 # CHECK: mfc0 $8, $16, 4
 0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
+0x41 0x00 0x01 0x4d # CHECK: bc0f 1336
+0x41 0x01 0x01 0x4d # CHECK: bc0t 1336
 0x41 0x60 0x60 0x00 # CHECK: di
 0x41 0x60 0x60 0x20 # CHECK: ei
 0x41 0x6e 0x60 0x20 # CHECK: ei $14
Index: test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
+++ test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
@@ -13,6 +13,8 @@
 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
 0x24 0xb8 0x4c 0x00 # CHECK: and $23, $2, $12
 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
+0x4d 0x01 0x00 0x41 # CHECK: bc0f 1336
+0x4d 0x01 0x01 0x41 # CHECK: bc0t 1336
 0x01 0x00 0x00 0x45 # CHECK: bc1f 8
 0x00 0x00 0x04 0x45 # CHECK: bc1f $fcc1, 4
 0x06 0x00 0x1e 0x45 # CHECK: bc1fl $fcc7, 28
Index: test/MC/Disassembler/Mips/mips4/valid-mips4.txt
===================================================================
--- test/MC/Disassembler/Mips/mips4/valid-mips4.txt
+++ test/MC/Disassembler/Mips/mips4/valid-mips4.txt
@@ -136,6 +136,8 @@
 0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4
 0x3a 0x00 0x27 0x12 # CHECK: xori $zero, $16, 10002       
 0x3c 0x00 0x00 0x80 # CHECK: lui $zero, 128
+0x41 0x00 0x01 0x4d # CHECK: bc0f 1336
+0x41 0x01 0x01 0x4d # CHECK: bc0t 1336
 0x42 0x00 0x00 0x01 # CHECK: tlbr
 0x42 0x00 0x00 0x02 # CHECK: tlbwi
 0x42 0x00 0x00 0x06 # CHECK: tlbwr
Index: test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
+++ test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
@@ -10,6 +10,8 @@
 0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
 0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
 0x4c 0x01 0x00 0x10 # CHECK: b 1332
+0x4d 0x01 0x00 0x41 # CHECK: bc0f 1336
+0x4d 0x01 0x01 0x41 # CHECK: bc0t 1336
 0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
Index: test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
+++ test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
@@ -14,6 +14,8 @@
 0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
 0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
 0x4c 0x01 0x00 0x10 # CHECK: b 1332
+0x4d 0x01 0x00 0x41 # CHECK: bc0f 1336
+0x4d 0x01 0x01 0x41 # CHECK: bc0t 1336
 0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
Index: test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
+++ test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
@@ -11,6 +11,8 @@
 0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
 0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
 0x4c 0x01 0x00 0x10 # CHECK: b 1332
+0x4d 0x01 0x00 0x41 # CHECK: bc0f 1336
+0x4d 0x01 0x01 0x41 # CHECK: bc0t 1336
 0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
Index: test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
+++ test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
@@ -11,6 +11,8 @@
 0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
 0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
 0x4c 0x01 0x00 0x10 # CHECK: b 1332
+0x4d 0x01 0x00 0x41 # CHECK: bc0f 1336
+0x4d 0x01 0x01 0x41 # CHECK: bc0t 1336
 0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
Index: test/MC/Mips/mips1/valid.s
===================================================================
--- test/MC/Mips/mips1/valid.s
+++ test/MC/Mips/mips1/valid.s
@@ -16,6 +16,8 @@
         addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         and       $s7,$v0,$12
         and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc0f      4                    # CHECK: bc0f 4        # encoding: [0x41,0x00,0x00,0x01]
+        bc0t      4                    # CHECK: bc0t 4        # encoding: [0x41,0x01,0x00,0x01]
         bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1t      $fcc0, 4             # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
Index: test/MC/Mips/mips2/valid.s
===================================================================
--- test/MC/Mips/mips2/valid.s
+++ test/MC/Mips/mips2/valid.s
@@ -16,6 +16,8 @@
         addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         and       $s7,$v0,$12
         and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc0f      4                    # CHECK: bc0f 4        # encoding: [0x41,0x00,0x00,0x01]
+        bc0t      4                    # CHECK: bc0t 4        # encoding: [0x41,0x01,0x00,0x01]
         bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1fl     $fcc0,50             # CHECK: bc1fl 50      # encoding: [0x45,0x02,0x00,0x0c]
Index: test/MC/Mips/mips3/valid.s
===================================================================
--- test/MC/Mips/mips3/valid.s
+++ test/MC/Mips/mips3/valid.s
@@ -16,6 +16,8 @@
         addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         and       $s7,$v0,$12
         and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc0f      4                    # CHECK: bc0f 4        # encoding: [0x41,0x00,0x00,0x01]
+        bc0t      4                    # CHECK: bc0t 4        # encoding: [0x41,0x01,0x00,0x01]
         bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1fl     $fcc0,50             # CHECK: bc1fl 50      # encoding: [0x45,0x02,0x00,0x0c]
Index: test/MC/Mips/mips32/valid.s
===================================================================
--- test/MC/Mips/mips32/valid.s
+++ test/MC/Mips/mips32/valid.s
@@ -16,6 +16,8 @@
         addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         and       $s7,$v0,$12
         and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc0f      4                    # CHECK: bc0f 4        # encoding: [0x41,0x00,0x00,0x01]
+        bc0t      4                    # CHECK: bc0t 4        # encoding: [0x41,0x01,0x00,0x01]
         bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
         bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
Index: test/MC/Mips/mips32r2/valid.s
===================================================================
--- test/MC/Mips/mips32r2/valid.s
+++ test/MC/Mips/mips32r2/valid.s
@@ -16,6 +16,8 @@
         addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         and       $s7,$v0,$12
         and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc0f      4                    # CHECK: bc0f 4        # encoding: [0x41,0x00,0x00,0x01]
+        bc0t      4                    # CHECK: bc0t 4        # encoding: [0x41,0x01,0x00,0x01]
         bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
         bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
Index: test/MC/Mips/mips32r3/valid.s
===================================================================
--- test/MC/Mips/mips32r3/valid.s
+++ test/MC/Mips/mips32r3/valid.s
@@ -16,6 +16,8 @@
         addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         and       $s7,$v0,$12
         and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc0f      4                    # CHECK: bc0f 4        # encoding: [0x41,0x00,0x00,0x01]
+        bc0t      4                    # CHECK: bc0t 4        # encoding: [0x41,0x01,0x00,0x01]
         bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
         bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
Index: test/MC/Mips/mips32r5/valid.s
===================================================================
--- test/MC/Mips/mips32r5/valid.s
+++ test/MC/Mips/mips32r5/valid.s
@@ -16,6 +16,8 @@
         addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         and       $s7,$v0,$12
         and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc0f      4                    # CHECK: bc0f 4        # encoding: [0x41,0x00,0x00,0x01]
+        bc0t      4                    # CHECK: bc0t 4        # encoding: [0x41,0x01,0x00,0x01]
         bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
         bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
Index: test/MC/Mips/mips4/valid.s
===================================================================
--- test/MC/Mips/mips4/valid.s
+++ test/MC/Mips/mips4/valid.s
@@ -16,6 +16,8 @@
         addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         and       $s7,$v0,$12
         and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc0f      4                    # CHECK: bc0f 4        # encoding: [0x41,0x00,0x00,0x01]
+        bc0t      4                    # CHECK: bc0t 4        # encoding: [0x41,0x01,0x00,0x01]
         bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
         bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
Index: test/MC/Mips/mips5/valid.s
===================================================================
--- test/MC/Mips/mips5/valid.s
+++ test/MC/Mips/mips5/valid.s
@@ -16,6 +16,8 @@
         addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         and       $s7,$v0,$12
         and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc0f      4                    # CHECK: bc0f 4        # encoding: [0x41,0x00,0x00,0x01]
+        bc0t      4                    # CHECK: bc0t 4        # encoding: [0x41,0x01,0x00,0x01]
         bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
         bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
Index: test/MC/Mips/mips64/valid.s
===================================================================
--- test/MC/Mips/mips64/valid.s
+++ test/MC/Mips/mips64/valid.s
@@ -16,6 +16,8 @@
         addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         and       $s7,$v0,$12
         and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc0f      4                    # CHECK: bc0f 4        # encoding: [0x41,0x00,0x00,0x01]
+        bc0t      4                    # CHECK: bc0t 4        # encoding: [0x41,0x01,0x00,0x01]
         bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
         bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
Index: test/MC/Mips/mips64r2/valid.s
===================================================================
--- test/MC/Mips/mips64r2/valid.s
+++ test/MC/Mips/mips64r2/valid.s
@@ -16,6 +16,8 @@
         addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         and       $s7,$v0,$12
         and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc0f      4                    # CHECK: bc0f 4        # encoding: [0x41,0x00,0x00,0x01]
+        bc0t      4                    # CHECK: bc0t 4        # encoding: [0x41,0x01,0x00,0x01]
         bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
         bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
Index: test/MC/Mips/mips64r3/valid.s
===================================================================
--- test/MC/Mips/mips64r3/valid.s
+++ test/MC/Mips/mips64r3/valid.s
@@ -16,6 +16,8 @@
         addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         and       $s7,$v0,$12
         and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc0f      4                    # CHECK: bc0f 4        # encoding: [0x41,0x00,0x00,0x01]
+        bc0t      4                    # CHECK: bc0t 4        # encoding: [0x41,0x01,0x00,0x01]
         bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
         bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
Index: test/MC/Mips/mips64r5/valid.s
===================================================================
--- test/MC/Mips/mips64r5/valid.s
+++ test/MC/Mips/mips64r5/valid.s
@@ -16,6 +16,8 @@
         addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         and       $s7,$v0,$12
         and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc0f      4                    # CHECK: bc0f 4        # encoding: [0x41,0x00,0x00,0x01]
+        bc0t      4                    # CHECK: bc0t 4        # encoding: [0x41,0x01,0x00,0x01]
         bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
         bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
         bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]