Index: lib/Target/Mips/MipsISelLowering.h =================================================================== --- lib/Target/Mips/MipsISelLowering.h +++ lib/Target/Mips/MipsISelLowering.h @@ -362,12 +362,12 @@ void analyzeCallOperands(const SmallVectorImpl &Outs, bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode, - std::vector &FuncArgs); + std::vector &FuncArgs, + CCState &State); void analyzeFormalArguments(const SmallVectorImpl &Ins, bool IsSoftFloat, - Function::const_arg_iterator FuncArg); - - const CCState &getCCInfo() const { return CCInfo; } + Function::const_arg_iterator FuncArg, + CCState &State); /// hasByValArg - Returns true if function has byval arguments. bool hasByValArg() const { return !ByValArgs.empty(); } @@ -386,7 +386,7 @@ private: void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, - ISD::ArgFlagsTy ArgFlags); + ISD::ArgFlagsTy ArgFlags, CCState &State); /// useRegsForByval - Returns true if the calling convention allows the /// use of registers to pass byval arguments. @@ -394,8 +394,8 @@ const MCPhysReg *shadowRegs() const; - void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, - unsigned Align); + void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, unsigned Align, + CCState &State); /// Return the type of the register which is used to pass an argument or /// return a value. This function returns f64 if the argument is an i64 @@ -406,7 +406,6 @@ SpecialCallingConvType getSpecialCallingConv(const SDNode *Callee) const; - CCState &CCInfo; CallingConv::ID CallConv; const MipsSubtarget &Subtarget; SmallVector ByValArgs; @@ -500,7 +499,8 @@ /// to the stack. Also create a stack frame object for the first variable /// argument. void writeVarArgRegs(std::vector &OutChains, const MipsCC &CC, - SDValue Chain, SDLoc DL, SelectionDAG &DAG) const; + SDValue Chain, SDLoc DL, SelectionDAG &DAG, + CCState &State) const; SDValue LowerFormalArguments(SDValue Chain, Index: lib/Target/Mips/MipsISelLowering.cpp =================================================================== --- lib/Target/Mips/MipsISelLowering.cpp +++ lib/Target/Mips/MipsISelLowering.cpp @@ -2550,9 +2550,8 @@ *DAG.getContext()); MipsCC MipsCCInfo(CallConv, Subtarget, CCInfo); - MipsCCInfo.analyzeCallOperands(Outs, IsVarArg, - Subtarget.abiUsesSoftFloat(), - Callee.getNode(), CLI.getArgs()); + MipsCCInfo.analyzeCallOperands(Outs, IsVarArg, Subtarget.abiUsesSoftFloat(), + Callee.getNode(), CLI.getArgs(), CCInfo); // Get a count of how many bytes are to be pushed on the stack. unsigned NextStackOffset = CCInfo.getNextStackOffset(); @@ -2837,7 +2836,7 @@ DAG.getMachineFunction().getFunction()->arg_begin(); bool UseSoftFloat = Subtarget.abiUsesSoftFloat(); - MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg); + MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg, CCInfo); MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), MipsCCInfo.hasByValArg()); @@ -2943,7 +2942,7 @@ } if (IsVarArg) - writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG); + writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG, CCInfo); // All stores are grouped in one node to allow the matching between // the size of Ins and InVals. This only happens when on varg functions @@ -3531,16 +3530,15 @@ MipsTargetLowering::MipsCC::MipsCC(CallingConv::ID CC, const MipsSubtarget &Subtarget_, CCState &Info) - : CCInfo(Info), CallConv(CC), Subtarget(Subtarget_) { + : CallConv(CC), Subtarget(Subtarget_) { // Pre-allocate reserved argument area. - CCInfo.AllocateStack(reservedArgArea(), 1); + Info.AllocateStack(reservedArgArea(), 1); } - -void MipsTargetLowering::MipsCC:: -analyzeCallOperands(const SmallVectorImpl &Args, - bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode, - std::vector &FuncArgs) { +void MipsTargetLowering::MipsCC::analyzeCallOperands( + const SmallVectorImpl &Args, bool IsVarArg, + bool IsSoftFloat, const SDNode *CallNode, + std::vector &FuncArgs, CCState &State) { MipsCC::SpecialCallingConvType SpecialCallingConv = getSpecialCallingConv(CallNode); assert((CallConv != CallingConv::Fast || !IsVarArg) && @@ -3558,16 +3556,16 @@ bool R; if (ArgFlags.isByVal()) { - handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); + handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, State); continue; } if (IsVarArg && !Args[I].IsFixed) - R = CC_Mips_VarArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); + R = CC_Mips_VarArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, State); else { MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode, IsSoftFloat); - R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo); + R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, State); } if (R) { @@ -3580,9 +3578,9 @@ } } -void MipsTargetLowering::MipsCC:: -analyzeFormalArguments(const SmallVectorImpl &Args, - bool IsSoftFloat, Function::const_arg_iterator FuncArg) { +void MipsTargetLowering::MipsCC::analyzeFormalArguments( + const SmallVectorImpl &Args, bool IsSoftFloat, + Function::const_arg_iterator FuncArg, CCState &State) { unsigned NumArgs = Args.size(); unsigned CurArgIdx = 0; @@ -3593,13 +3591,13 @@ CurArgIdx = Args[I].OrigArgIndex; if (ArgFlags.isByVal()) { - handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); + handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, State); continue; } MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), nullptr, IsSoftFloat); - if (!CC_Mips_FixedArg(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo)) + if (!CC_Mips_FixedArg(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, State)) continue; #ifndef NDEBUG @@ -3613,7 +3611,8 @@ void MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, - ISD::ArgFlagsTy ArgFlags) { + ISD::ArgFlagsTy ArgFlags, + CCState &State) { assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0."); struct ByValArgInfo ByVal; @@ -3624,13 +3623,13 @@ RegSizeInBytes * 2); if (useRegsForByval()) - allocateRegs(ByVal, ByValSize, Align); + allocateRegs(ByVal, ByValSize, Align, State); // Allocate space on caller's stack. ByVal.Address = - CCInfo.AllocateStack(ByValSize - RegSizeInBytes * ByVal.NumRegs, Align); - CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT, - LocInfo)); + State.AllocateStack(ByValSize - RegSizeInBytes * ByVal.NumRegs, Align); + State.addLoc( + CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT, LocInfo)); ByValArgs.push_back(ByVal); } @@ -3650,7 +3649,7 @@ void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, - unsigned Align) { + unsigned Align, CCState &State) { unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); const ArrayRef IntArgRegs = intArgRegs(); const MCPhysReg *ShadowRegs = shadowRegs(); @@ -3659,18 +3658,18 @@ "RegSizeInBytes."); ByVal.FirstIdx = - CCInfo.getFirstUnallocated(IntArgRegs.data(), IntArgRegs.size()); + State.getFirstUnallocated(IntArgRegs.data(), IntArgRegs.size()); // If Align > RegSizeInBytes, the first arg register must be even. if ((Align > RegSizeInBytes) && (ByVal.FirstIdx % 2)) { - CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]); + State.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]); ++ByVal.FirstIdx; } // Mark the registers allocated. for (unsigned I = ByVal.FirstIdx; ByValSize && (I < IntArgRegs.size()); ByValSize -= RegSizeInBytes, ++I, ++ByVal.NumRegs) - CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]); + State.AllocateReg(IntArgRegs[I], ShadowRegs[I]); } MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy, @@ -3833,10 +3832,10 @@ void MipsTargetLowering::writeVarArgRegs(std::vector &OutChains, const MipsCC &CC, SDValue Chain, - SDLoc DL, SelectionDAG &DAG) const { + SDLoc DL, SelectionDAG &DAG, + CCState &State) const { const ArrayRef ArgRegs = CC.intArgRegs(); - const CCState &CCInfo = CC.getCCInfo(); - unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs.data(), ArgRegs.size()); + unsigned Idx = State.getFirstUnallocated(ArgRegs.data(), ArgRegs.size()); unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); const TargetRegisterClass *RC = getRegClassFor(RegTy); @@ -3849,7 +3848,7 @@ if (ArgRegs.size() == Idx) VaArgOffset = - RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSizeInBytes); + RoundUpToAlignment(State.getNextStackOffset(), RegSizeInBytes); else VaArgOffset = (int)CC.reservedArgArea() - (int)(RegSizeInBytes * (ArgRegs.size() - Idx));