Index: lib/CodeGen/DeadMachineInstructionElim.cpp =================================================================== --- lib/CodeGen/DeadMachineInstructionElim.cpp +++ lib/CodeGen/DeadMachineInstructionElim.cpp @@ -10,7 +10,9 @@ // //===----------------------------------------------------------------------===// +#include "llvm/ADT/DenseSet.h" #include "llvm/ADT/Statistic.h" +#include "llvm/CodeGen/LiveIntervals.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" @@ -32,6 +34,7 @@ const TargetRegisterInfo *TRI; const MachineRegisterInfo *MRI; const TargetInstrInfo *TII; + LiveIntervals *LIS; BitVector LivePhysRegs; public: @@ -41,7 +44,7 @@ } void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.setPreservesCFG(); + AU.setPreservesAll(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -78,9 +81,15 @@ unsigned Reg = MO.getReg(); if (TargetRegisterInfo::isPhysicalRegister(Reg)) { // Don't delete live physreg defs, or any reserved register defs. - if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg)) + // Do not remove physreg defs if we have LIS as we may be unable + // to accurately recompute its liveness. + if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg) || LIS) return false; } else { + // An instruction can also use its def in case if it is a tied operand. + // TODO: Technically we can also remove it if def dominates the use. + // This can happen when two instructions define different subregs + // of the same register. for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) { if (&Use != MI) // This def has a non-debug use. Don't delete the instruction! @@ -102,6 +111,8 @@ MRI = &MF.getRegInfo(); TRI = MF.getSubtarget().getRegisterInfo(); TII = MF.getSubtarget().getInstrInfo(); + LIS = getAnalysisIfAvailable(); + DenseSet RecalcRegs; // Loop over all instructions in all blocks, from bottom to top, so that it's // more likely that chains of dependent but ultimately dead instructions will @@ -127,6 +138,14 @@ // If the instruction is dead, delete it! if (isDead(MI)) { LLVM_DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI); + if (LIS) { + for (const MachineOperand &MO : MI->operands()) { + if (MO.isReg() && TRI->isVirtualRegister(MO.getReg())) + RecalcRegs.insert(MO.getReg()); + } + LIS->RemoveMachineInstrFromMaps(*MI); + } + // It is possible that some DBG_VALUE instructions refer to this // instruction. They get marked as undef and will be deleted // in the live debug variable analysis. @@ -170,5 +189,12 @@ } LivePhysRegs.clear(); + + for (auto Reg : RecalcRegs) { + LIS->removeInterval(Reg); + if (!MRI->reg_empty(Reg)) + LIS->createAndComputeVirtRegInterval(Reg); + } + return AnyChanges; } Index: lib/CodeGen/TargetPassConfig.cpp =================================================================== --- lib/CodeGen/TargetPassConfig.cpp +++ lib/CodeGen/TargetPassConfig.cpp @@ -158,6 +158,12 @@ static cl::opt EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline")); +// Option is used in lit tests to prevent deadcoding of patterns inspected. +static cl::opt +DisableDCEInRA("disable-dce-in-ra", + cl::init(false), cl::Hidden, + cl::desc("Disable machine DCE inside regalloc")); + // Experimental option to use CFL-AA in codegen enum class CFLAAType { None, Steensgaard, Andersen, Both }; static cl::opt UseCFLAA( @@ -1163,6 +1169,9 @@ // separate vregs before. Splitting can also improve reg. allocation quality. addPass(&RenameIndependentSubregsID); + if (!DisableDCEInRA) + addPass(&DeadMachineInstructionElimID); + // PreRA instruction scheduling. addPass(&MachineSchedulerID); Index: test/CodeGen/AArch64/O3-pipeline.ll =================================================================== --- test/CodeGen/AArch64/O3-pipeline.ll +++ test/CodeGen/AArch64/O3-pipeline.ll @@ -114,6 +114,7 @@ ; CHECK-NEXT: Live Interval Analysis ; CHECK-NEXT: Simple Register Coalescing ; CHECK-NEXT: Rename Disconnected Subregister Components +; CHECK-NEXT: Remove dead machine instructions ; CHECK-NEXT: Machine Instruction Scheduler ; CHECK-NEXT: Machine Block Frequency Analysis ; CHECK-NEXT: Debug Variable Analysis Index: test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll =================================================================== --- test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll +++ test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=apple -aarch64-enable-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-NOOPT -; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=apple -aarch64-enable-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-OPT -; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic -aarch64-enable-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-NOOPT -; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic -aarch64-enable-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-OPT +; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=apple -aarch64-enable-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true -disable-dce-in-ra | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-NOOPT +; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=apple -aarch64-enable-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false -disable-dce-in-ra | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-OPT +; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic -aarch64-enable-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true -disable-dce-in-ra | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-NOOPT +; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic -aarch64-enable-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false -disable-dce-in-ra | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-OPT define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone { ; CHECK-LABEL: bar: Index: test/CodeGen/AMDGPU/dead-lane.mir =================================================================== --- /dev/null +++ test/CodeGen/AMDGPU/dead-lane.mir @@ -0,0 +1,24 @@ +# RUN: llc -march=amdgcn -mcpu=tonga %s -start-before detect-dead-lanes -stop-before machine-scheduler -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s + +# GCN-LABEL: name: dead_lane +# GCN: bb.0: +# GCN-NEXT: undef %3.sub0:vreg_64 = V_MAC_F32_e32 undef %0:vgpr_32, undef %0:vgpr_32, undef %3.sub0, implicit $exec +# GCN-NEXT: FLAT_STORE_DWORD undef %4:vreg_64, %3.sub0, +--- +name: dead_lane +tracksRegLiveness: true +registers: + - { id: 0, class: vgpr_32} + - { id: 1, class: vgpr_32} + - { id: 2, class: vgpr_32} + - { id: 3, class: vreg_64} + - { id: 4, class: vreg_64} +body: | + bb.0: + %1:vgpr_32 = V_MAC_F32_e32 undef %0, undef %0, undef %0, implicit $exec + %2:vgpr_32 = V_MAC_F32_e32 undef %0, undef %0, undef %0, implicit $exec + %3:vreg_64 = REG_SEQUENCE %1, %subreg.sub0, %2, %subreg.sub1 + FLAT_STORE_DWORD undef %4, %3.sub0, 0, 0, 0, implicit $exec, implicit $flat_scr + S_ENDPGM 0 + +... Index: test/CodeGen/AMDGPU/salu-to-valu.ll =================================================================== --- test/CodeGen/AMDGPU/salu-to-valu.ll +++ test/CodeGen/AMDGPU/salu-to-valu.ll @@ -475,6 +475,7 @@ bb4: %tmp5 = phi i32 [ %tmp3, %bb2 ], [ %tmp, %bb1 ] + store volatile i32 %tmp5, i32 addrspace(1)* undef br label %bb1 } Index: test/CodeGen/AMDGPU/sdwa-peephole.ll =================================================================== --- test/CodeGen/AMDGPU/sdwa-peephole.ll +++ test/CodeGen/AMDGPU/sdwa-peephole.ll @@ -523,5 +523,6 @@ bb11: ; preds = %bb10, %bb2 %tmp12 = phi <2 x i32> [ %tmp6, %bb2 ], [ %tmp, %bb1 ] + store volatile <2 x i32> %tmp12, <2 x i32> addrspace(1)* undef br label %bb1 } Index: test/CodeGen/AMDGPU/shrink-carry.mir =================================================================== --- test/CodeGen/AMDGPU/shrink-carry.mir +++ test/CodeGen/AMDGPU/shrink-carry.mir @@ -21,6 +21,7 @@ %2 = IMPLICIT_DEF %3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec %4, %5 = V_SUBBREV_U32_e64 0, %0, %3, 0, implicit $exec + GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, 0, implicit $exec ... @@ -45,6 +46,7 @@ %2 = IMPLICIT_DEF %3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec %4, %5 = V_SUBB_U32_e64 %0, 0, %3, 0, implicit $exec + GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, 0, implicit $exec ... @@ -69,6 +71,7 @@ %2 = IMPLICIT_DEF %3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec %4, %5 = V_ADDC_U32_e64 0, %0, %3, 0, implicit $exec + GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, 0, implicit $exec ... @@ -93,5 +96,6 @@ %2 = IMPLICIT_DEF %3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec %4, %5 = V_ADDC_U32_e64 %0, 0, %3, 0, implicit $exec + GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, 0, implicit $exec ... Index: test/CodeGen/AMDGPU/spill-empty-live-interval.mir =================================================================== --- test/CodeGen/AMDGPU/spill-empty-live-interval.mir +++ test/CodeGen/AMDGPU/spill-empty-live-interval.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -disable-dce-in-ra -verify-machineinstrs -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy -o - %s | FileCheck %s # https://bugs.llvm.org/show_bug.cgi?id=33620 --- Index: test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll =================================================================== --- test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll +++ test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=tahiti -o - %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=tahiti -disable-dce-in-ra -o - %s | FileCheck %s ; Don't crash when the use of an undefined value is only detected by the ; register coalescer because it is hidden with subregister insert/extract. target triple="amdgcn--" Index: test/CodeGen/ARM/select-imm.ll =================================================================== --- test/CodeGen/ARM/select-imm.ll +++ test/CodeGen/ARM/select-imm.ll @@ -1,15 +1,15 @@ -; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s --check-prefix=ARM +; RUN: llc -mtriple=arm-eabi -disable-dce-in-ra %s -o - | FileCheck %s --check-prefix=ARM -; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \ +; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 -disable-dce-in-ra %s -o - \ ; RUN: | FileCheck %s --check-prefix=ARMT2 -; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m0 %s -o - \ +; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m0 -disable-dce-in-ra %s -o - \ ; RUN: | FileCheck %s --check-prefix=THUMB1 -; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \ +; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 -disable-dce-in-ra %s -o - \ ; RUN: | FileCheck %s --check-prefix=THUMB2 -; RUN: llc -mtriple=thumbv8m.base-eabi %s -o - \ +; RUN: llc -mtriple=thumbv8m.base-eabi -disable-dce-in-ra %s -o - \ ; RUN: | FileCheck %s --check-prefix=V8MBASE define i32 @t1(i32 %c) nounwind readnone { Index: test/CodeGen/Hexagon/v6-unaligned-spill.ll =================================================================== --- test/CodeGen/Hexagon/v6-unaligned-spill.ll +++ test/CodeGen/Hexagon/v6-unaligned-spill.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -march=hexagon -disable-dce-in-ra < %s | FileCheck %s ; Test that we generate an unaligned vector store for a spill when a function ; has an alloca. Also, make sure the addressing mode for unaligned store does Index: test/CodeGen/X86/O3-pipeline.ll =================================================================== --- test/CodeGen/X86/O3-pipeline.ll +++ test/CodeGen/X86/O3-pipeline.ll @@ -111,6 +111,7 @@ ; CHECK-NEXT: Live Interval Analysis ; CHECK-NEXT: Simple Register Coalescing ; CHECK-NEXT: Rename Disconnected Subregister Components +; CHECK-NEXT: Remove dead machine instructions ; CHECK-NEXT: Machine Instruction Scheduler ; CHECK-NEXT: Machine Block Frequency Analysis ; CHECK-NEXT: Debug Variable Analysis Index: test/CodeGen/X86/combine-bitselect.ll =================================================================== --- test/CodeGen/X86/combine-bitselect.ll +++ test/CodeGen/X86/combine-bitselect.ll @@ -612,41 +612,23 @@ ; ; XOP-LABEL: bitselect_v4i1_loop: ; XOP: # %bb.0: # %bb -; XOP-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; XOP-NEXT: vpcomneqd %xmm1, %xmm0, %xmm1 -; XOP-NEXT: vpcomeqd {{.*}}(%rip), %xmm0, %xmm0 -; XOP-NEXT: vmovdqa %xmm1, %xmm2 ; XOP-NEXT: .p2align 4, 0x90 ; XOP-NEXT: .LBB12_1: # %bb1 ; XOP-NEXT: # =>This Inner Loop Header: Depth=1 -; XOP-NEXT: vblendvps %xmm1, %xmm0, %xmm2, %xmm2 ; XOP-NEXT: jmp .LBB12_1 ; ; AVX1-LABEL: bitselect_v4i1_loop: ; AVX1: # %bb.0: # %bb -; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm1 -; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 -; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm2 -; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: .p2align 4, 0x90 ; AVX1-NEXT: .LBB12_1: # %bb1 ; AVX1-NEXT: # =>This Inner Loop Header: Depth=1 -; AVX1-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm2 ; AVX1-NEXT: jmp .LBB12_1 ; ; AVX2-LABEL: bitselect_v4i1_loop: ; AVX2: # %bb.0: # %bb -; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm1 -; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 -; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm2 -; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [12,12,12,12] -; AVX2-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm0 ; AVX2-NEXT: .p2align 4, 0x90 ; AVX2-NEXT: .LBB12_1: # %bb1 ; AVX2-NEXT: # =>This Inner Loop Header: Depth=1 -; AVX2-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm2 ; AVX2-NEXT: jmp .LBB12_1 ; ; AVX512F-LABEL: bitselect_v4i1_loop: Index: test/CodeGen/X86/llc-start-stop-instance.ll =================================================================== --- test/CodeGen/X86/llc-start-stop-instance.ll +++ test/CodeGen/X86/llc-start-stop-instance.ll @@ -1,18 +1,18 @@ -; RUN: llc -mtriple=x86_64-- -debug-pass=Structure -stop-after=dead-mi-elimination,1 %s -o /dev/null 2>&1 \ +; RUN: llc -mtriple=x86_64-- -debug-pass=Structure -stop-after=dead-mi-elimination,1 -disable-dce-in-ra %s -o /dev/null 2>&1 \ ; RUN: | FileCheck -check-prefix=STOP-AFTER-DEAD1 %s -; RUN: llc -mtriple=x86_64-- -debug-pass=Structure -stop-after=dead-mi-elimination,0 %s -o /dev/null 2>&1 \ +; RUN: llc -mtriple=x86_64-- -debug-pass=Structure -stop-after=dead-mi-elimination,0 -disable-dce-in-ra %s -o /dev/null 2>&1 \ ; RUN: | FileCheck -check-prefix=STOP-AFTER-DEAD0 %s -; RUN: llc -mtriple=x86_64-- -debug-pass=Structure -stop-before=dead-mi-elimination,1 %s -o /dev/null 2>&1 \ +; RUN: llc -mtriple=x86_64-- -debug-pass=Structure -stop-before=dead-mi-elimination,1 -disable-dce-in-ra %s -o /dev/null 2>&1 \ ; RUN: | FileCheck -check-prefix=STOP-BEFORE-DEAD1 %s -; RUN: llc -mtriple=x86_64-- -debug-pass=Structure -start-before=dead-mi-elimination,1 %s -o /dev/null 2>&1 \ +; RUN: llc -mtriple=x86_64-- -debug-pass=Structure -start-before=dead-mi-elimination,1 -disable-dce-in-ra %s -o /dev/null 2>&1 \ ; RUN: | FileCheck -check-prefix=START-BEFORE-DEAD1 %s -; RUN: llc -mtriple=x86_64-- -debug-pass=Structure -start-after=dead-mi-elimination,1 %s -o /dev/null 2>&1 \ +; RUN: llc -mtriple=x86_64-- -debug-pass=Structure -start-after=dead-mi-elimination,1 -disable-dce-in-ra %s -o /dev/null 2>&1 \ ; RUN: | FileCheck -check-prefix=START-AFTER-DEAD1 %s Index: test/CodeGen/X86/speculative-load-hardening-gather.ll =================================================================== --- test/CodeGen/X86/speculative-load-hardening-gather.ll +++ test/CodeGen/X86/speculative-load-hardening-gather.ll @@ -7,7 +7,6 @@ ; CHECK-LABEL: test_llvm_x86_avx2_gather_d_ps: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; CHECK-NEXT: orq %rax, %rdi @@ -30,7 +29,6 @@ ; CHECK-LABEL: test_llvm_x86_avx2_gather_q_ps: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; CHECK-NEXT: orq %rax, %rdi @@ -53,7 +51,6 @@ ; CHECK-LABEL: test_llvm_x86_avx2_gather_d_pd: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2 ; CHECK-NEXT: orq %rax, %rdi @@ -76,7 +73,6 @@ ; CHECK-LABEL: test_llvm_x86_avx2_gather_q_pd: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2 ; CHECK-NEXT: orq %rax, %rdi @@ -99,7 +95,6 @@ ; CHECK-LABEL: test_llvm_x86_avx2_gather_d_ps_256: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; CHECK-NEXT: orq %rax, %rdi @@ -122,7 +117,6 @@ ; CHECK-LABEL: test_llvm_x86_avx2_gather_q_ps_256: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; CHECK-NEXT: orq %rax, %rdi @@ -146,7 +140,6 @@ ; CHECK-LABEL: test_llvm_x86_avx2_gather_d_pd_256: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2 ; CHECK-NEXT: orq %rax, %rdi @@ -169,7 +162,6 @@ ; CHECK-LABEL: test_llvm_x86_avx2_gather_q_pd_256: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2 ; CHECK-NEXT: orq %rax, %rdi @@ -192,7 +184,6 @@ ; CHECK-LABEL: test_llvm_x86_avx2_gather_d_d: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; CHECK-NEXT: orq %rax, %rdi @@ -215,7 +206,6 @@ ; CHECK-LABEL: test_llvm_x86_avx2_gather_q_d: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; CHECK-NEXT: orq %rax, %rdi @@ -238,7 +228,6 @@ ; CHECK-LABEL: test_llvm_x86_avx2_gather_d_q: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; CHECK-NEXT: orq %rax, %rdi @@ -261,7 +250,6 @@ ; CHECK-LABEL: test_llvm_x86_avx2_gather_q_q: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; CHECK-NEXT: orq %rax, %rdi @@ -284,7 +272,6 @@ ; CHECK-LABEL: test_llvm_x86_avx2_gather_d_d_256: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; CHECK-NEXT: orq %rax, %rdi @@ -307,7 +294,6 @@ ; CHECK-LABEL: test_llvm_x86_avx2_gather_q_d_256: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; CHECK-NEXT: orq %rax, %rdi @@ -331,7 +317,6 @@ ; CHECK-LABEL: test_llvm_x86_avx2_gather_d_q_256: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; CHECK-NEXT: orq %rax, %rdi @@ -354,7 +339,6 @@ ; CHECK-LABEL: test_llvm_x86_avx2_gather_q_q_256: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; CHECK-NEXT: orq %rax, %rdi @@ -377,7 +361,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather_dps_512: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 @@ -400,7 +383,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather_dpd_512: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1 @@ -424,7 +406,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather_qps_512: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 @@ -447,7 +428,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather_qpd_512: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1 @@ -470,7 +450,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather_dpi_512: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 @@ -493,7 +472,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather_dpq_512: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 @@ -518,7 +496,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather_qpi_512: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 @@ -541,7 +518,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather_qpq_512: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 @@ -564,7 +540,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gatherpf_qps_512: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: orq %rax, %rdi @@ -586,7 +561,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather3siv4_sf: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 @@ -609,7 +583,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather3div4_sf: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 @@ -632,7 +605,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather3siv2_df: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1 @@ -655,7 +627,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather3div2_df: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1 @@ -678,7 +649,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather3siv8_sf: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 @@ -701,7 +671,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather3div8_sf: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 @@ -725,7 +694,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather3siv4_df: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1 @@ -748,7 +716,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather3div4_df: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1 @@ -771,7 +738,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather3siv4_si: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 @@ -794,7 +760,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather3div4_si: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 @@ -817,7 +782,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather3siv2_di: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 @@ -840,7 +804,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather3div2_di: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 @@ -863,7 +826,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather3siv8_si: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 @@ -886,7 +848,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather3div8_si: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 @@ -910,7 +871,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather3siv4_di: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 @@ -933,7 +893,6 @@ ; CHECK-LABEL: test_llvm_x86_avx512_gather3div4_di: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rsp, %rax -; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 Index: test/CodeGen/X86/speculative-load-hardening-indirect.ll =================================================================== --- test/CodeGen/X86/speculative-load-hardening-indirect.ll +++ test/CodeGen/X86/speculative-load-hardening-indirect.ll @@ -53,7 +53,7 @@ ; X64-PIC-NEXT: movq %rsp, %rcx ; X64-PIC-NEXT: movq -{{[0-9]+}}(%rsp), %rdx ; X64-PIC-NEXT: sarq $63, %rcx -; X64-PIC-NEXT: leaq .Lslh_ret_addr0(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rbx, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -92,7 +92,6 @@ ; X64-LABEL: test_indirect_tail_call: ; X64: # %bb.0: # %entry ; X64-NEXT: movq %rsp, %rax -; X64-NEXT: movq $-1, %rcx ; X64-NEXT: sarq $63, %rax ; X64-NEXT: movq (%rdi), %rcx ; X64-NEXT: orq %rax, %rcx @@ -103,7 +102,6 @@ ; X64-PIC-LABEL: test_indirect_tail_call: ; X64-PIC: # %bb.0: # %entry ; X64-PIC-NEXT: movq %rsp, %rax -; X64-PIC-NEXT: movq $-1, %rcx ; X64-PIC-NEXT: sarq $63, %rax ; X64-PIC-NEXT: movq (%rdi), %rcx ; X64-PIC-NEXT: orq %rax, %rcx @@ -114,7 +112,6 @@ ; X64-RETPOLINE-LABEL: test_indirect_tail_call: ; X64-RETPOLINE: # %bb.0: # %entry ; X64-RETPOLINE-NEXT: movq %rsp, %rax -; X64-RETPOLINE-NEXT: movq $-1, %rcx ; X64-RETPOLINE-NEXT: sarq $63, %rax ; X64-RETPOLINE-NEXT: movq (%rdi), %r11 ; X64-RETPOLINE-NEXT: orq %rax, %r11 @@ -134,7 +131,7 @@ ; X64-NEXT: movq %rsp, %rax ; X64-NEXT: movq $-1, %rbx ; X64-NEXT: sarq $63, %rax -; X64-NEXT: movq global_fnptr(%rip), %rcx +; X64-NEXT: movq {{.*}}(%rip), %rcx ; X64-NEXT: orq %rax, %rcx ; X64-NEXT: shlq $47, %rax ; X64-NEXT: orq %rax, %rsp @@ -156,7 +153,7 @@ ; X64-PIC-NEXT: movq %rsp, %rax ; X64-PIC-NEXT: movq $-1, %rbx ; X64-PIC-NEXT: sarq $63, %rax -; X64-PIC-NEXT: movq global_fnptr@GOTPCREL(%rip), %rcx +; X64-PIC-NEXT: movq global_fnptr@{{.*}}(%rip), %rcx ; X64-PIC-NEXT: movq (%rcx), %rcx ; X64-PIC-NEXT: orq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rax @@ -166,7 +163,7 @@ ; X64-PIC-NEXT: movq %rsp, %rcx ; X64-PIC-NEXT: movq -{{[0-9]+}}(%rsp), %rdx ; X64-PIC-NEXT: sarq $63, %rcx -; X64-PIC-NEXT: leaq .Lslh_ret_addr1(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rbx, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -180,7 +177,7 @@ ; X64-RETPOLINE-NEXT: movq %rsp, %rax ; X64-RETPOLINE-NEXT: movq $-1, %rbx ; X64-RETPOLINE-NEXT: sarq $63, %rax -; X64-RETPOLINE-NEXT: movq global_fnptr(%rip), %r11 +; X64-RETPOLINE-NEXT: movq {{.*}}(%rip), %r11 ; X64-RETPOLINE-NEXT: shlq $47, %rax ; X64-RETPOLINE-NEXT: orq %rax, %rsp ; X64-RETPOLINE-NEXT: callq __llvm_retpoline_r11 @@ -204,9 +201,8 @@ ; X64-LABEL: test_indirect_tail_call_global: ; X64: # %bb.0: # %entry ; X64-NEXT: movq %rsp, %rax -; X64-NEXT: movq $-1, %rcx ; X64-NEXT: sarq $63, %rax -; X64-NEXT: movq global_fnptr(%rip), %rcx +; X64-NEXT: movq {{.*}}(%rip), %rcx ; X64-NEXT: orq %rax, %rcx ; X64-NEXT: shlq $47, %rax ; X64-NEXT: orq %rax, %rsp @@ -215,9 +211,8 @@ ; X64-PIC-LABEL: test_indirect_tail_call_global: ; X64-PIC: # %bb.0: # %entry ; X64-PIC-NEXT: movq %rsp, %rax -; X64-PIC-NEXT: movq $-1, %rcx ; X64-PIC-NEXT: sarq $63, %rax -; X64-PIC-NEXT: movq global_fnptr@GOTPCREL(%rip), %rcx +; X64-PIC-NEXT: movq global_fnptr@{{.*}}(%rip), %rcx ; X64-PIC-NEXT: movq (%rcx), %rcx ; X64-PIC-NEXT: orq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rax @@ -227,9 +222,8 @@ ; X64-RETPOLINE-LABEL: test_indirect_tail_call_global: ; X64-RETPOLINE: # %bb.0: # %entry ; X64-RETPOLINE-NEXT: movq %rsp, %rax -; X64-RETPOLINE-NEXT: movq $-1, %rcx ; X64-RETPOLINE-NEXT: sarq $63, %rax -; X64-RETPOLINE-NEXT: movq global_fnptr(%rip), %r11 +; X64-RETPOLINE-NEXT: movq {{.*}}(%rip), %r11 ; X64-RETPOLINE-NEXT: shlq $47, %rax ; X64-RETPOLINE-NEXT: orq %rax, %rsp ; X64-RETPOLINE-NEXT: jmp __llvm_retpoline_r11 # TAILCALL @@ -291,7 +285,7 @@ ; X64-PIC-NEXT: jmpq *%rdx ; X64-PIC-NEXT: .LBB4_1: # Block address taken ; X64-PIC-NEXT: # %bb0 -; X64-PIC-NEXT: leaq .LBB4_1(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -300,7 +294,7 @@ ; X64-PIC-NEXT: retq ; X64-PIC-NEXT: .LBB4_3: # Block address taken ; X64-PIC-NEXT: # %bb2 -; X64-PIC-NEXT: leaq .LBB4_3(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -309,7 +303,7 @@ ; X64-PIC-NEXT: retq ; X64-PIC-NEXT: .LBB4_4: # Block address taken ; X64-PIC-NEXT: # %bb3 -; X64-PIC-NEXT: leaq .LBB4_4(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -318,7 +312,7 @@ ; X64-PIC-NEXT: retq ; X64-PIC-NEXT: .LBB4_2: # Block address taken ; X64-PIC-NEXT: # %bb1 -; X64-PIC-NEXT: leaq .LBB4_2(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -394,13 +388,13 @@ ; X64-PIC-NEXT: movq $-1, %rax ; X64-PIC-NEXT: sarq $63, %rcx ; X64-PIC-NEXT: movslq %edi, %rdx -; X64-PIC-NEXT: movq global_blockaddrs@GOTPCREL(%rip), %rsi +; X64-PIC-NEXT: movq global_blockaddrs@{{.*}}(%rip), %rsi ; X64-PIC-NEXT: movq (%rsi,%rdx,8), %rdx ; X64-PIC-NEXT: orq %rcx, %rdx ; X64-PIC-NEXT: jmpq *%rdx ; X64-PIC-NEXT: .Ltmp0: # Block address taken ; X64-PIC-NEXT: .LBB5_1: # %bb0 -; X64-PIC-NEXT: leaq .LBB5_1(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -409,7 +403,7 @@ ; X64-PIC-NEXT: retq ; X64-PIC-NEXT: .Ltmp1: # Block address taken ; X64-PIC-NEXT: .LBB5_3: # %bb2 -; X64-PIC-NEXT: leaq .LBB5_3(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -418,7 +412,7 @@ ; X64-PIC-NEXT: retq ; X64-PIC-NEXT: .Ltmp2: # Block address taken ; X64-PIC-NEXT: .LBB5_4: # %bb3 -; X64-PIC-NEXT: leaq .LBB5_4(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -427,7 +421,7 @@ ; X64-PIC-NEXT: retq ; X64-PIC-NEXT: .Ltmp3: # Block address taken ; X64-PIC-NEXT: .LBB5_2: # %bb1 -; X64-PIC-NEXT: leaq .LBB5_2(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -564,14 +558,14 @@ ; X64-PIC-NEXT: # %bb.1: # %entry ; X64-PIC-NEXT: cmovaq %rax, %rcx ; X64-PIC-NEXT: movl %edi, %edx -; X64-PIC-NEXT: leaq .LJTI6_0(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: movslq (%rsi,%rdx,4), %rdx ; X64-PIC-NEXT: addq %rsi, %rdx ; X64-PIC-NEXT: orq %rcx, %rdx ; X64-PIC-NEXT: jmpq *%rdx ; X64-PIC-NEXT: .LBB6_3: # Block address taken ; X64-PIC-NEXT: # %bb1 -; X64-PIC-NEXT: leaq .LBB6_3(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -586,7 +580,7 @@ ; X64-PIC-NEXT: retq ; X64-PIC-NEXT: .LBB6_4: # Block address taken ; X64-PIC-NEXT: # %bb2 -; X64-PIC-NEXT: leaq .LBB6_4(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -595,7 +589,7 @@ ; X64-PIC-NEXT: retq ; X64-PIC-NEXT: .LBB6_5: # Block address taken ; X64-PIC-NEXT: # %bb3 -; X64-PIC-NEXT: leaq .LBB6_5(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -604,7 +598,7 @@ ; X64-PIC-NEXT: retq ; X64-PIC-NEXT: .LBB6_6: # Block address taken ; X64-PIC-NEXT: # %bb5 -; X64-PIC-NEXT: leaq .LBB6_6(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -753,7 +747,7 @@ ; X64-PIC-NEXT: cmovaq %r10, %r9 ; X64-PIC-NEXT: xorl %eax, %eax ; X64-PIC-NEXT: movl %edi, %esi -; X64-PIC-NEXT: leaq .LJTI7_0(%rip), %rdi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rdi ; X64-PIC-NEXT: movslq (%rdi,%rsi,4), %rsi ; X64-PIC-NEXT: addq %rdi, %rsi ; X64-PIC-NEXT: orq %r9, %rsi @@ -762,34 +756,34 @@ ; X64-PIC-NEXT: cmovbeq %r10, %r9 ; X64-PIC-NEXT: movl (%rsi), %eax ; X64-PIC-NEXT: orl %r9d, %eax -; X64-PIC-NEXT: leaq .LBB7_3(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: .LBB7_3: # Block address taken ; X64-PIC-NEXT: # %bb1 -; X64-PIC-NEXT: leaq .LBB7_3(%rip), %rdi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rdi ; X64-PIC-NEXT: cmpq %rdi, %rsi ; X64-PIC-NEXT: cmovneq %r10, %r9 ; X64-PIC-NEXT: addl (%rdx), %eax ; X64-PIC-NEXT: orl %r9d, %eax -; X64-PIC-NEXT: leaq .LBB7_4(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: .LBB7_4: # Block address taken ; X64-PIC-NEXT: # %bb2 -; X64-PIC-NEXT: leaq .LBB7_4(%rip), %rdx +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rdx ; X64-PIC-NEXT: cmpq %rdx, %rsi ; X64-PIC-NEXT: cmovneq %r10, %r9 ; X64-PIC-NEXT: addl (%rcx), %eax ; X64-PIC-NEXT: orl %r9d, %eax -; X64-PIC-NEXT: leaq .LBB7_5(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: .LBB7_5: # Block address taken ; X64-PIC-NEXT: # %bb3 -; X64-PIC-NEXT: leaq .LBB7_5(%rip), %rcx +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rcx ; X64-PIC-NEXT: cmpq %rcx, %rsi ; X64-PIC-NEXT: cmovneq %r10, %r9 ; X64-PIC-NEXT: addl (%r8), %eax ; X64-PIC-NEXT: orl %r9d, %eax -; X64-PIC-NEXT: leaq .LBB7_6(%rip), %rsi +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi ; X64-PIC-NEXT: .LBB7_6: # Block address taken ; X64-PIC-NEXT: # %bb4 -; X64-PIC-NEXT: leaq .LBB7_6(%rip), %rcx +; X64-PIC-NEXT: leaq {{.*}}(%rip), %rcx ; X64-PIC-NEXT: cmpq %rcx, %rsi ; X64-PIC-NEXT: cmovneq %r10, %r9 ; X64-PIC-NEXT: shlq $47, %r9 Index: test/CodeGen/X86/speculative-load-hardening.ll =================================================================== --- test/CodeGen/X86/speculative-load-hardening.ll +++ test/CodeGen/X86/speculative-load-hardening.ll @@ -12,7 +12,6 @@ ; X64-LABEL: test_trivial_entry_load: ; X64: # %bb.0: # %entry ; X64-NEXT: movq %rsp, %rcx -; X64-NEXT: movq $-1, %rax ; X64-NEXT: sarq $63, %rcx ; X64-NEXT: movl (%rdi), %eax ; X64-NEXT: orl %ecx, %eax Index: test/CodeGen/X86/tail-dup-merge-loop-headers.ll =================================================================== --- test/CodeGen/X86/tail-dup-merge-loop-headers.ll +++ test/CodeGen/X86/tail-dup-merge-loop-headers.ll @@ -124,9 +124,8 @@ ; CHECK-NEXT: cmpl $4, %r14d ; CHECK-NEXT: jb .LBB1_28 ; CHECK-NEXT: # %bb.6: # %shared_preheader -; CHECK-NEXT: movb $32, %dl +; CHECK-NEXT: movb $32, %cl ; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: # implicit-def: $rcx ; CHECK-NEXT: testl %ebp, %ebp ; CHECK-NEXT: je .LBB1_18 ; CHECK-NEXT: .p2align 4, 0x90 @@ -144,9 +143,9 @@ ; CHECK-NEXT: jae .LBB1_22 ; CHECK-NEXT: # %bb.11: # %if.end287.i ; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=1 -; CHECK-NEXT: xorl %esi, %esi +; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: cmpl $1, %ebp -; CHECK-NEXT: setne %dl +; CHECK-NEXT: setne %cl ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: jne .LBB1_15 ; CHECK-NEXT: # %bb.12: # %if.end308.i @@ -155,31 +154,29 @@ ; CHECK-NEXT: je .LBB1_17 ; CHECK-NEXT: # %bb.13: # %if.end335.i ; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=1 -; CHECK-NEXT: xorl %edx, %edx -; CHECK-NEXT: testb %dl, %dl -; CHECK-NEXT: movl $0, %esi +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: testb %cl, %cl +; CHECK-NEXT: movl $0, %edx ; CHECK-NEXT: jne .LBB1_7 ; CHECK-NEXT: # %bb.14: # %merge_other ; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=1 -; CHECK-NEXT: xorl %esi, %esi +; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: jmp .LBB1_16 ; CHECK-NEXT: .LBB1_15: # in Loop: Header=BB1_8 Depth=1 -; CHECK-NEXT: movb %dl, %sil -; CHECK-NEXT: addl $3, %esi +; CHECK-NEXT: movb %cl, %dl +; CHECK-NEXT: addl $3, %edx ; CHECK-NEXT: .LBB1_16: # %outer_loop_latch ; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=1 -; CHECK-NEXT: # implicit-def: $dl +; CHECK-NEXT: # implicit-def: $cl ; CHECK-NEXT: jmp .LBB1_7 ; CHECK-NEXT: .LBB1_17: # %merge_predecessor_split ; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=1 -; CHECK-NEXT: movb $32, %dl -; CHECK-NEXT: xorl %esi, %esi +; CHECK-NEXT: movb $32, %cl +; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: .LBB1_7: # %outer_loop_latch ; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=1 -; CHECK-NEXT: movzwl %si, %esi -; CHECK-NEXT: decl %esi -; CHECK-NEXT: movzwl %si, %esi -; CHECK-NEXT: leaq 1(%rcx,%rsi), %rcx +; CHECK-NEXT: movzwl %dx, %edx +; CHECK-NEXT: decl %edx ; CHECK-NEXT: testl %ebp, %ebp ; CHECK-NEXT: jne .LBB1_8 ; CHECK-NEXT: .LBB1_18: # %while.cond.us1412.i @@ -188,7 +185,7 @@ ; CHECK-NEXT: movl $1, %ebx ; CHECK-NEXT: jne .LBB1_20 ; CHECK-NEXT: # %bb.19: # %while.cond.us1412.i -; CHECK-NEXT: decb %dl +; CHECK-NEXT: decb %cl ; CHECK-NEXT: jne .LBB1_26 ; CHECK-NEXT: .LBB1_20: # %if.end41.us1436.i ; CHECK-NEXT: .LBB1_25: