diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -68,6 +68,7 @@
   case ISD::ZERO_EXTEND_VECTOR_INREG:
     R = ScalarizeVecRes_VecInregOp(N);
     break;
+  case ISD::ABS:
   case ISD::ANY_EXTEND:
   case ISD::BITREVERSE:
   case ISD::BSWAP:
diff --git a/llvm/test/CodeGen/WebAssembly/PR41149.ll b/llvm/test/CodeGen/WebAssembly/PR41149.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/PR41149.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s
+
+; Regression test for PR41149.
+
+target triple = "wasm32-unknown--unknown"
+
+define void @mod() {
+entry:
+  %tmp = load <4 x i8>, <4 x i8>* undef
+  %tmp2 = icmp slt <4 x i8> %tmp, zeroinitializer
+  %tmp3 = sub <4 x i8> zeroinitializer, %tmp
+  %tmp4 = select <4 x i1> %tmp2, <4 x i8> %tmp3, <4 x i8> %tmp
+  store <4 x i8> %tmp4, <4 x i8>* undef
+  ret void
+}