Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -1192,9 +1192,9 @@
   let Inst{11-15} = DCMX{4-0};
   let Inst{16-20} = XB{4-0};
   let Inst{21-24} = xo1;
-  let Inst{25}    = DCMX{5};
+  let Inst{25}    = DCMX{6};
   let Inst{26-28} = xo2;
-  let Inst{29}    = DCMX{6};
+  let Inst{29}    = DCMX{5};
   let Inst{30}    = XB{5};
   let Inst{31}    = XT{5};
 }
Index: llvm/test/MC/Disassembler/PowerPC/vsx.txt
===================================================================
--- llvm/test/MC/Disassembler/PowerPC/vsx.txt
+++ llvm/test/MC/Disassembler/PowerPC/vsx.txt
@@ -853,3 +853,9 @@
 
 # CHECK: mfvsrld 3, 34
 0x7c 0x43 0x02 0x67
+
+# CHECK: xvtstdcdp 63, 63, 65
+0xf3 0xe1 0xff 0xeb
+
+# CHECK: xvtstdcsp 63, 63, 34
+0xf3 0xe2 0xfe 0xaf
Index: llvm/test/MC/PowerPC/vsx.s
===================================================================
--- llvm/test/MC/PowerPC/vsx.s
+++ llvm/test/MC/PowerPC/vsx.s
@@ -948,3 +948,10 @@
 # CHECK-BE: mfvsrld 3, 34                      # encoding: [0x7c,0x43,0x02,0x67]
 # CHECK-LE: mfvsrld 3, 34                      # encoding: [0x67,0x02,0x43,0x7c]
             mfvsrld 3, 34
+
+# CHECK-BE: xvtstdcdp 63, 63, 65               # encoding: [0xf3,0xe1,0xff,0xeb]
+# CHECK-LE: xvtstdcdp 63, 63, 65               # encoding: [0xeb,0xff,0xe1,0xf3]
+            xvtstdcdp 63, 63, 65
+# CHECK-BE: xvtstdcsp 63, 63, 34               # encoding: [0xf3,0xe2,0xfe,0xaf]
+# CHECK-LE: xvtstdcsp 63, 63, 34               # encoding: [0xaf,0xfe,0xe2,0xf3]
+            xvtstdcsp 63, 63, 34