Index: lib/Target/Mips/MipsDSPInstrInfo.td =================================================================== --- lib/Target/Mips/MipsDSPInstrInfo.td +++ lib/Target/Mips/MipsDSPInstrInfo.td @@ -1313,7 +1313,9 @@ def PseudoPICK_PH : PseudoPICK; def PseudoPICK_QB : PseudoPICK; -def PseudoMTLOHI_DSP : PseudoMTLOHI; +let AdditionalPredicates = [HasDSP] in { + def PseudoMTLOHI_DSP : PseudoMTLOHI; +} // Patterns. class DSPPat : Index: lib/Target/Mips/MipsSEInstrInfo.cpp =================================================================== --- lib/Target/Mips/MipsSEInstrInfo.cpp +++ lib/Target/Mips/MipsSEInstrInfo.cpp @@ -446,6 +446,9 @@ case Mips::PseudoMTLOHI_DSP: expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true); break; + case Mips::PseudoMTLOHI_MM: + expandPseudoMTLoHi(MBB, MI, Mips::MTLO_MM, Mips::MTHI_MM, false); + break; case Mips::PseudoCVT_S_W: expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); break; Index: test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll =================================================================== --- /dev/null +++ test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll @@ -0,0 +1,90 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+micromips -asm-show-inst < %s |\ +; RUN: FileCheck %s -check-prefixes=MMR2 +; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+dsp,+micromips -asm-show-inst < %s |\ +; RUN: FileCheck %s -check-prefixes=MMR2-DSP +; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s |\ +; RUN: FileCheck %s -check-prefixes=MMR6 + +define i64 @test(i32 signext %a, i32 signext %b) { +; MMR2-LABEL: test: +; MMR2: # %bb.0: # %entry +; MMR2-NEXT: li16 $2, 0 # +; MMR2-NEXT: # > +; MMR2-NEXT: li16 $3, 1 # +; MMR2-NEXT: # > +; MMR2-NEXT: mtlo $3 # > +; MMR2-NEXT: mthi $2 # > +; MMR2-NEXT: madd $4, $5 # +; MMR2-NEXT: # > +; MMR2-NEXT: mflo16 $2 # > +; MMR2-NEXT: mfhi16 $3 # > +; MMR2-NEXT: jrc $ra # > +; +; MMR2-DSP-LABEL: test: +; MMR2-DSP: # %bb.0: # %entry +; MMR2-DSP-NEXT: li16 $2, 0 # +; MMR2-DSP-NEXT: # > +; MMR2-DSP-NEXT: li16 $3, 1 # +; MMR2-DSP-NEXT: # > +; MMR2-DSP-NEXT: mtlo $3, $ac0 # +; MMR2-DSP-NEXT: # > +; MMR2-DSP-NEXT: mthi $2, $ac0 # +; MMR2-DSP-NEXT: # > +; MMR2-DSP-NEXT: madd $ac0, $4, $5 # +; MMR2-DSP-NEXT: # +; MMR2-DSP-NEXT: # +; MMR2-DSP-NEXT: # > +; MMR2-DSP-NEXT: mflo $2, $ac0 # +; MMR2-DSP-NEXT: # > +; MMR2-DSP-NEXT: jr $ra # > +; MMR2-DSP-NEXT: mfhi $3, $ac0 # +; MMR2-DSP-NEXT: # > +; +; MMR6-LABEL: test: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: mul $3, $4, $5 # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: addiur2 $2, $3, 1 # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: sltu $3, $2, $3 # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: muh $4, $4, $5 # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: addu16 $3, $4, $3 # +; MMR6-NEXT: # +; MMR6-NEXT: # > +; MMR6-NEXT: jrc $ra # > +entry: + %conv = sext i32 %a to i64 + %conv1 = sext i32 %b to i64 + %mul = mul nsw i64 %conv, %conv1 + %add = add nsw i64 %mul, 1 + ret i64 %add +} Index: test/CodeGen/Mips/micromips-pseudo-mtlohi-match.ll =================================================================== --- /dev/null +++ test/CodeGen/Mips/micromips-pseudo-mtlohi-match.ll @@ -0,0 +1,57 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +; RUN: llc -stop-before=expand-isel-pseudos -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s |\ +; RUN: FileCheck %s -check-prefixes=MMR2 +; RUN: llc -stop-before=expand-isel-pseudos -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+dsp,+micromips < %s |\ +; RUN: FileCheck %s -check-prefixes=MMR2-DSP +; RUN: llc -stop-before=expand-isel-pseudos -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s |\ +; RUN: FileCheck %s -check-prefixes=MMR6 + +define i64 @test(i32 signext %a, i32 signext %b) { + ; MMR2-LABEL: name: test + ; MMR2: bb.0.entry: + ; MMR2: liveins: $a0, $a1 + ; MMR2: [[COPY:%[0-9]+]]:gpr32 = COPY $a1 + ; MMR2: [[COPY1:%[0-9]+]]:gpr32 = COPY $a0 + ; MMR2: [[LI16_MM:%[0-9]+]]:gprmm16 = LI16_MM 0 + ; MMR2: [[LI16_MM1:%[0-9]+]]:gprmm16 = LI16_MM 1 + ; MMR2: [[PseudoMTLOHI_MM:%[0-9]+]]:acc64 = PseudoMTLOHI_MM killed [[LI16_MM1]], killed [[LI16_MM]] + ; MMR2: [[PseudoMADD_MM:%[0-9]+]]:acc64 = PseudoMADD_MM [[COPY1]], [[COPY]], [[PseudoMTLOHI_MM]] + ; MMR2: [[PseudoMFHI_MM:%[0-9]+]]:gpr32 = PseudoMFHI_MM [[PseudoMADD_MM]] + ; MMR2: [[PseudoMFLO_MM:%[0-9]+]]:gpr32 = PseudoMFLO_MM [[PseudoMADD_MM]] + ; MMR2: $v0 = COPY [[PseudoMFHI_MM]] + ; MMR2: $v1 = COPY [[PseudoMFLO_MM]] + ; MMR2: RetRA implicit $v0, implicit $v1 + ; MMR2-DSP-LABEL: name: test + ; MMR2-DSP: bb.0.entry: + ; MMR2-DSP: liveins: $a0, $a1 + ; MMR2-DSP: [[COPY:%[0-9]+]]:gpr32 = COPY $a1 + ; MMR2-DSP: [[COPY1:%[0-9]+]]:gpr32 = COPY $a0 + ; MMR2-DSP: [[LI16_MM:%[0-9]+]]:gprmm16 = LI16_MM 0 + ; MMR2-DSP: [[LI16_MM1:%[0-9]+]]:gprmm16 = LI16_MM 1 + ; MMR2-DSP: [[PseudoMTLOHI_DSP:%[0-9]+]]:acc64dsp = PseudoMTLOHI_DSP killed [[LI16_MM1]], killed [[LI16_MM]] + ; MMR2-DSP: [[MADD_DSP:%[0-9]+]]:acc64dsp = MADD_DSP [[COPY1]], [[COPY]], [[PseudoMTLOHI_DSP]] + ; MMR2-DSP: [[MFHI_DSP:%[0-9]+]]:gpr32 = MFHI_DSP [[MADD_DSP]] + ; MMR2-DSP: [[MFLO_DSP:%[0-9]+]]:gpr32 = MFLO_DSP [[MADD_DSP]] + ; MMR2-DSP: $v0 = COPY [[MFHI_DSP]] + ; MMR2-DSP: $v1 = COPY [[MFLO_DSP]] + ; MMR2-DSP: RetRA implicit $v0, implicit $v1 + ; MMR6-LABEL: name: test + ; MMR6: bb.0.entry: + ; MMR6: liveins: $a0, $a1 + ; MMR6: [[COPY:%[0-9]+]]:gpr32 = COPY $a1 + ; MMR6: [[COPY1:%[0-9]+]]:gpr32 = COPY $a0 + ; MMR6: [[MUL_MMR6_:%[0-9]+]]:gprmm16 = MUL_MMR6 [[COPY1]], [[COPY]] + ; MMR6: [[ADDIUR2_MM:%[0-9]+]]:gprmm16 = ADDIUR2_MM [[MUL_MMR6_]], 1 + ; MMR6: [[SLTu_MM:%[0-9]+]]:gprmm16 = SLTu_MM [[ADDIUR2_MM]], [[MUL_MMR6_]] + ; MMR6: [[MUH_MMR6_:%[0-9]+]]:gprmm16 = MUH_MMR6 [[COPY1]], [[COPY]] + ; MMR6: [[ADDU16_MMR6_:%[0-9]+]]:gprmm16 = ADDU16_MMR6 killed [[MUH_MMR6_]], killed [[SLTu_MM]] + ; MMR6: $v0 = COPY [[ADDU16_MMR6_]] + ; MMR6: $v1 = COPY [[ADDIUR2_MM]] + ; MMR6: RetRA implicit $v0, implicit $v1 +entry: + %conv = sext i32 %a to i64 + %conv1 = sext i32 %b to i64 + %mul = mul nsw i64 %conv, %conv1 + %add = add nsw i64 %mul, 1 + ret i64 %add +}