Index: lib/CodeGen/TargetRegisterInfo.cpp
===================================================================
--- lib/CodeGen/TargetRegisterInfo.cpp
+++ lib/CodeGen/TargetRegisterInfo.cpp
@@ -13,6 +13,7 @@
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
@@ -397,6 +398,7 @@
   const std::pair<unsigned, SmallVector<unsigned, 4>> &Hints_MRI =
     MRI.getRegAllocationHints(VirtReg);
 
+  SmallSet<unsigned, 32> HintedRegs;
   // First hint may be a target hint.
   bool Skip = (Hints_MRI.first != 0);
   for (auto Reg : Hints_MRI.second) {
@@ -410,6 +412,10 @@
     if (VRM && isVirtualRegister(Phys))
       Phys = VRM->getPhys(Phys);
 
+    // Don't add the same reg twice (Hints_MRI may contain multiple virtual
+    // registers allocated to the same physreg.
+    if (!HintedRegs.insert(Phys).second)
+      continue;
     // Check that Phys is a valid hint in VirtReg's register class.
     if (!isPhysicalRegister(Phys))
       continue;
Index: test/CodeGen/X86/regalloc-copy-hints.mir
===================================================================
--- /dev/null
+++ test/CodeGen/X86/regalloc-copy-hints.mir
@@ -0,0 +1,805 @@
+# RUN: llc -mtriple=i386-unknown-unknown -mcpu=i486 %s -o - -run-pass greedy \
+# RUN:   -debug-only=regalloc 2>&1 | FileCheck %s
+# REQUIRES: asserts
+
+--- |
+  %0 = type { %1 }
+  %1 = type { %2, %23, %23*, %27*, %28*, %29, %33*, %34, %42, i8, i32, i32, i32 }
+  %2 = type { %3, %6, %14, %14, i8, i8*, i8*, %16 }
+  %3 = type { i32 (...)**, %4*, %5* }
+  %4 = type { i32 (...)**, %3* }
+  %5 = type { i32 (...)** }
+  %6 = type { %7 }
+  %7 = type { %8, i32, %12 }
+  %8 = type { %9**, %9**, %9**, %10 }
+  %9 = type { i32, i32, i32, i8* }
+  %10 = type { %11 }
+  %11 = type { %9** }
+  %12 = type { %13 }
+  %13 = type { i32 }
+  %14 = type { i32, %15* }
+  %15 = type { i32, i32, i8* }
+  %16 = type { %17 }
+  %17 = type { %18*, %20, %22 }
+  %18 = type { %19* }
+  %19 = type <{ %18, %19*, %18*, i8, [3 x i8] }>
+  %20 = type { %21 }
+  %21 = type { %18 }
+  %22 = type { %13 }
+  %23 = type { %24 }
+  %24 = type { %18*, %25, %26 }
+  %25 = type { %21 }
+  %26 = type { %13 }
+  %27 = type { i32 (...)** }
+  %28 = type { i32 (...)** }
+  %29 = type { %30 }
+  %30 = type { %18*, %31, %32 }
+  %31 = type { %21 }
+  %32 = type { %13 }
+  %33 = type { i32 (...)** }
+  %34 = type { %35 }
+  %35 = type { %36 }
+  %36 = type { %37, i32, %41 }
+  %37 = type { %38**, %38**, %38**, %39 }
+  %38 = type { %42, i32 }
+  %39 = type { %40 }
+  %40 = type { %38** }
+  %41 = type { %13 }
+  %42 = type { %43 }
+  %43 = type { %18*, %44, %45 }
+  %44 = type { %21 }
+  %45 = type { %13 }
+  %46 = type { %47, %48 }
+  %47 = type <{ %18, %19*, %18*, i8 }>
+  %48 = type { %49 }
+  %49 = type { i32, %50 }
+  %50 = type { { i32, i32 }, { i32, i32 }, { i32, i32 }, { i32, i32 }, { i32, i32 }, { i32, i32 } }
+  
+  define void @fun(%0* %arg) local_unnamed_addr #0 align 2 personality i32 (...)* @__gxx_personality_v0 {
+  bb:
+    %tmp = getelementptr inbounds %0, %0* %arg, i32 0, i32 0, i32 1
+    %tmp1 = getelementptr inbounds %0, %0* %arg, i32 0, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0
+    br i1 undef, label %bb5, label %bb6
+  
+  bb5:                                              ; preds = %bb
+    unreachable
+  
+  bb6:                                              ; preds = %bb
+    %tmp8 = getelementptr inbounds %0, %0* %arg, i32 0, i32 0, i32 8, i32 0, i32 1, i32 0, i32 0
+    br i1 undef, label %bb10, label %bb9
+  
+  bb9:                                              ; preds = %bb6
+    unreachable
+  
+  bb10:                                             ; preds = %bb6
+    store %18* %tmp8, %18** undef
+    br i1 undef, label %bb14, label %bb13
+  
+  bb13:                                             ; preds = %bb10
+    unreachable
+  
+  bb14:                                             ; preds = %bb10
+    br i1 undef, label %bb17, label %bb18
+  
+  bb17:                                             ; preds = %bb14
+    unreachable
+  
+  bb18:                                             ; preds = %bb14
+    br i1 undef, label %bb20, label %bb19
+  
+  bb19:                                             ; preds = %bb18
+    unreachable
+  
+  bb20:                                             ; preds = %bb18
+    br i1 undef, label %bb25, label %bb24
+  
+  bb24:                                             ; preds = %bb20
+    unreachable
+  
+  bb25:                                             ; preds = %bb20
+    br i1 undef, label %bb29, label %bb30
+  
+  bb29:                                             ; preds = %bb25
+    unreachable
+  
+  bb30:                                             ; preds = %bb25
+    br i1 undef, label %bb38, label %bb31
+  
+  bb31:                                             ; preds = %bb30
+    %tmp32 = getelementptr inbounds %0, %0* %arg, i32 0, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0, i32 0
+    br i1 undef, label %bb34, label %bb35
+  
+  bb34:                                             ; preds = %bb31
+    unreachable
+  
+  bb35:                                             ; preds = %bb31
+    br i1 undef, label %bb40, label %bb36
+  
+  bb36:                                             ; preds = %bb35
+    unreachable
+  
+  bb38:                                             ; preds = %bb30
+    %tmp391 = bitcast %18* %tmp1 to %19**
+    br label %bb40
+  
+  bb40:                                             ; preds = %bb35, %bb38
+    %tmp41 = phi %18* [ %tmp1, %bb38 ], [ null, %bb35 ]
+    %tmp42 = phi %19** [ %tmp391, %bb38 ], [ %tmp32, %bb35 ]
+    br i1 undef, label %bb43, label %bb48
+  
+  bb43:                                             ; preds = %bb40
+    %tmp44 = tail call i8* @_Znwj()
+    store %18* %tmp41, %18** undef
+    %tmp46 = bitcast %19** %tmp42 to i8**
+    store i8* %tmp44, i8** %tmp46
+    %0 = bitcast i8* %tmp44 to %46*
+    tail call void @_ZNSt3__127__tree_balance_after_insertIPNS_16__tree_node_baseIPvEEEEvT_S5_()
+    br label %bb48
+  
+  bb48:                                             ; preds = %bb43, %bb40
+    %tmp49 = phi %46* [ %0, %bb43 ], [ undef, %bb40 ]
+    %tmp50 = getelementptr inbounds %46, %46* %tmp49, i32 0, i32 1, i32 0, i32 1, i32 4, i32 0
+    store i32 ptrtoint (i1 (%0*)* @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private15_preEnd__authorEv to i32), i32* %tmp50
+    br i1 undef, label %bb52, label %bb53
+  
+  bb52:                                             ; preds = %bb48
+    unreachable
+  
+  bb53:                                             ; preds = %bb48
+    br i1 undef, label %bb55, label %bb54
+  
+  bb54:                                             ; preds = %bb53
+    unreachable
+  
+  bb55:                                             ; preds = %bb53
+    br i1 undef, label %bb59, label %bb58
+  
+  bb58:                                             ; preds = %bb55
+    unreachable
+  
+  bb59:                                             ; preds = %bb55
+    br i1 undef, label %bb62, label %bb61
+  
+  bb61:                                             ; preds = %bb59
+    unreachable
+  
+  bb62:                                             ; preds = %bb59
+    br i1 undef, label %bb64, label %bb65
+  
+  bb64:                                             ; preds = %bb62
+    unreachable
+  
+  bb65:                                             ; preds = %bb62
+    %tmp66 = icmp eq %46* null, null
+    br i1 %tmp66, label %bb72, label %bb67
+  
+  bb67:                                             ; preds = %bb65
+    %tmp68 = getelementptr inbounds %0, %0* %arg, i32 0, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0, i32 0
+    br i1 undef, label %bb70, label %bb74
+  
+  bb70:                                             ; preds = %bb67
+    unreachable
+  
+  bb72:                                             ; preds = %bb65
+    %tmp732 = bitcast %18* %tmp1 to %19**
+    br label %bb74
+  
+  bb74:                                             ; preds = %bb67, %bb72
+    %tmp75 = phi %18* [ %tmp1, %bb72 ], [ null, %bb67 ]
+    %tmp76 = phi %19** [ %tmp732, %bb72 ], [ %tmp68, %bb67 ]
+    %tmp77 = tail call i8* @_Znwj()
+    store %18* %tmp75, %18** undef
+    %tmp79 = bitcast %19** %tmp76 to i8**
+    store i8* %tmp77, i8** %tmp79
+    %1 = bitcast i8* %tmp77 to %46*
+    tail call void @_ZNSt3__127__tree_balance_after_insertIPNS_16__tree_node_baseIPvEEEEvT_S5_()
+    %tmp81 = getelementptr inbounds %46, %46* %1, i32 0, i32 1, i32 0, i32 1, i32 2, i32 0
+    store i32 ptrtoint (i1 (%0*)* @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private14_end__commentsEv to i32), i32* %tmp81
+    store %18* %tmp8, %18** undef
+    %2 = bitcast %0* %arg to i8*
+    %sunkaddr = getelementptr i8, i8* %2, i32 140
+    %3 = bitcast i8* %sunkaddr to %18**
+    %tmp85 = load %18*, %18** %3
+    %tmp864 = bitcast %18* %tmp85 to %19**
+    %tmp87 = load %19*, %19** %tmp864
+    %tmp88 = icmp eq %19* %tmp87, null
+    br i1 %tmp88, label %bb90, label %bb89
+  
+  bb89:                                             ; preds = %bb74
+    unreachable
+  
+  bb90:                                             ; preds = %bb74
+    br i1 undef, label %bb94, label %bb92
+  
+  bb92:                                             ; preds = %bb90
+    br i1 undef, label %bb96, label %bb97
+  
+  bb94:                                             ; preds = %bb90
+    unreachable
+  
+  bb96:                                             ; preds = %bb92
+    unreachable
+  
+  bb97:                                             ; preds = %bb92
+    br i1 undef, label %bb101, label %bb102
+  
+  bb101:                                            ; preds = %bb97
+    unreachable
+  
+  bb102:                                            ; preds = %bb97
+    br i1 undef, label %bb104, label %bb103
+  
+  bb103:                                            ; preds = %bb102
+    unreachable
+  
+  bb104:                                            ; preds = %bb102
+    br i1 undef, label %bb109, label %bb108
+  
+  bb108:                                            ; preds = %bb104
+    unreachable
+  
+  bb109:                                            ; preds = %bb104
+    br i1 undef, label %bb111, label %bb112
+  
+  bb111:                                            ; preds = %bb109
+    unreachable
+  
+  bb112:                                            ; preds = %bb109
+    br i1 undef, label %bb118, label %bb117
+  
+  bb117:                                            ; preds = %bb112
+    unreachable
+  
+  bb118:                                            ; preds = %bb112
+    br i1 undef, label %bb120, label %bb121
+  
+  bb120:                                            ; preds = %bb118
+    unreachable
+  
+  bb121:                                            ; preds = %bb118
+    br i1 undef, label %bb124, label %bb125
+  
+  bb124:                                            ; preds = %bb121
+    unreachable
+  
+  bb125:                                            ; preds = %bb121
+    %4 = bitcast %18* %tmp1 to %46**
+    %tmp126 = load %46*, %46** %4
+    %tmp127 = icmp eq %46* %tmp126, null
+    br i1 %tmp127, label %bb135, label %bb128
+  
+  bb128:                                            ; preds = %bb125
+    br label %bb129
+  
+  bb129:                                            ; preds = %bb131, %bb128
+    %tmp130 = icmp ugt i32 undef, 95406324
+    br i1 %tmp130, label %bb131, label %bb133
+  
+  bb131:                                            ; preds = %bb129
+    br label %bb129
+  
+  bb133:                                            ; preds = %bb129
+    unreachable
+  
+  bb135:                                            ; preds = %bb125
+    br i1 undef, label %bb137, label %bb138
+  
+  bb137:                                            ; preds = %bb135
+    unreachable
+  
+  bb138:                                            ; preds = %bb135
+    unreachable
+  }
+  
+  declare zeroext i1 @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private15_preEnd__authorEv(%0*) #0
+  
+  declare zeroext i1 @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private14_end__commentsEv(%0*) #0 align 2
+  
+  declare i32 @__gxx_personality_v0(...) #0
+  
+  declare noalias nonnull i8* @_Znwj() local_unnamed_addr #0
+  
+  declare void @_ZNSt3__127__tree_balance_after_insertIPNS_16__tree_node_baseIPvEEEEvT_S5_() local_unnamed_addr #0
+  
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**) #1
+  
+  attributes #0 = { "target-cpu"="i486" }
+  attributes #1 = { nounwind }
+
+...
+---
+# A physreg should always only be hinted once per getRegAllocationHints() query.
+# CHECK: hints: $ebx $edi
+# CHECK-NOT: hints: $ebx $edi $ebx $edi
+name:            fun
+alignment:       4
+tracksRegLiveness: true
+registers:       
+  - { id: 0, class: gr32 }
+  - { id: 1, class: gr32 }
+  - { id: 2, class: gr32 }
+  - { id: 3, class: gr32 }
+  - { id: 4, class: gr32 }
+  - { id: 5, class: gr32 }
+  - { id: 6, class: gr32 }
+  - { id: 7, class: gr32 }
+  - { id: 8, class: gr32 }
+  - { id: 9, class: gr32 }
+  - { id: 10, class: gr32 }
+  - { id: 11, class: gr32 }
+  - { id: 12, class: gr32 }
+  - { id: 13, class: gr32_abcd }
+  - { id: 14, class: gr8 }
+  - { id: 15, class: gr32_abcd }
+  - { id: 16, class: gr8 }
+  - { id: 17, class: gr32 }
+  - { id: 18, class: gr32_abcd }
+  - { id: 19, class: gr8 }
+  - { id: 20, class: gr32_abcd }
+  - { id: 21, class: gr8 }
+  - { id: 22, class: gr32_abcd }
+  - { id: 23, class: gr8 }
+  - { id: 24, class: gr32_abcd }
+  - { id: 25, class: gr8 }
+  - { id: 26, class: gr32_abcd }
+  - { id: 27, class: gr8 }
+  - { id: 28, class: gr32_abcd }
+  - { id: 29, class: gr8 }
+  - { id: 30, class: gr32_abcd }
+  - { id: 31, class: gr8 }
+  - { id: 32, class: gr32_abcd }
+  - { id: 33, class: gr8 }
+  - { id: 34, class: gr32 }
+  - { id: 35, class: gr32_abcd }
+  - { id: 36, class: gr8 }
+  - { id: 37, class: gr32 }
+  - { id: 38, class: gr32 }
+  - { id: 39, class: gr32_abcd }
+  - { id: 40, class: gr8 }
+  - { id: 41, class: gr32_abcd }
+  - { id: 42, class: gr8 }
+  - { id: 43, class: gr32_abcd }
+  - { id: 44, class: gr8 }
+  - { id: 45, class: gr32_abcd }
+  - { id: 46, class: gr8 }
+  - { id: 47, class: gr32_abcd }
+  - { id: 48, class: gr8 }
+  - { id: 49, class: gr8 }
+  - { id: 50, class: gr32_abcd }
+  - { id: 51, class: gr8 }
+  - { id: 52, class: gr32 }
+  - { id: 53, class: gr32 }
+  - { id: 54, class: gr32 }
+  - { id: 55, class: gr32 }
+  - { id: 56, class: gr32_abcd }
+  - { id: 57, class: gr8 }
+  - { id: 58, class: gr32_abcd }
+  - { id: 59, class: gr8 }
+  - { id: 60, class: gr32_abcd }
+  - { id: 61, class: gr8 }
+  - { id: 62, class: gr32_abcd }
+  - { id: 63, class: gr8 }
+  - { id: 64, class: gr32_abcd }
+  - { id: 65, class: gr8 }
+  - { id: 66, class: gr32_abcd }
+  - { id: 67, class: gr8 }
+  - { id: 68, class: gr32_abcd }
+  - { id: 69, class: gr8 }
+  - { id: 70, class: gr32_abcd }
+  - { id: 71, class: gr8 }
+  - { id: 72, class: gr32_abcd }
+  - { id: 73, class: gr8 }
+  - { id: 74, class: gr32 }
+  - { id: 75, class: gr32 }
+  - { id: 76, class: gr32_abcd }
+  - { id: 77, class: gr8 }
+  - { id: 78, class: gr32_abcd }
+  - { id: 79, class: gr32 }
+  - { id: 80, class: gr32 }
+  - { id: 81, class: gr32_abcd }
+  - { id: 82, class: gr32 }
+frameInfo:       
+  maxAlignment:    4
+  hasCalls:        true
+fixedStack:      
+  - { id: 0, size: 4, alignment: 4, stack-id: 0, isImmutable: true }
+body:             |
+  bb.0.bb:
+    successors: %bb.1(0x00000001), %bb.2(0x7fffffff)
+  
+    %13:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %13.sub_8bit, %13.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.2, implicit killed $eflags
+    JMP_1 %bb.1
+  
+  bb.1.bb5:
+    successors: 
+  
+  
+  bb.2.bb6:
+    successors: %bb.4(0x7fffffff), %bb.3(0x00000001)
+  
+    %15:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %15.sub_8bit, %15.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.4, implicit killed $eflags
+    JMP_1 %bb.3
+  
+  bb.3.bb9:
+    successors: 
+  
+  
+  bb.4.bb10:
+    successors: %bb.6(0x7fffffff), %bb.5(0x00000001)
+  
+    %12:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 4 from %fixed-stack.0)
+    %1:gr32 = LEA32r %12, 1, $noreg, 144, $noreg
+    MOV32mr undef %17:gr32, 1, $noreg, 0, $noreg, %1 :: (store 4 into `%18** undef`)
+    %18:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %18.sub_8bit, %18.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.6, implicit killed $eflags
+    JMP_1 %bb.5
+  
+  bb.5.bb13:
+    successors: 
+  
+  
+  bb.6.bb14:
+    successors: %bb.7(0x00000001), %bb.8(0x7fffffff)
+  
+    %20:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %20.sub_8bit, %20.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.8, implicit killed $eflags
+    JMP_1 %bb.7
+  
+  bb.7.bb17:
+    successors: 
+  
+  
+  bb.8.bb18:
+    successors: %bb.10(0x7fffffff), %bb.9(0x00000001)
+  
+    %22:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %22.sub_8bit, %22.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.10, implicit killed $eflags
+    JMP_1 %bb.9
+  
+  bb.9.bb19:
+    successors: 
+  
+  
+  bb.10.bb20:
+    successors: %bb.12(0x7fffffff), %bb.11(0x00000001)
+  
+    %24:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %24.sub_8bit, %24.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.12, implicit killed $eflags
+    JMP_1 %bb.11
+  
+  bb.11.bb24:
+    successors: 
+  
+  
+  bb.12.bb25:
+    successors: %bb.13(0x00000001), %bb.14(0x7fffffff)
+  
+    %26:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %26.sub_8bit, %26.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.14, implicit killed $eflags
+    JMP_1 %bb.13
+  
+  bb.13.bb29:
+    successors: 
+  
+  
+  bb.14.bb30:
+    %0:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
+    %28:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %28.sub_8bit, %28.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.20, implicit killed $eflags
+    JMP_1 %bb.15
+  
+  bb.15.bb31:
+    successors: %bb.16(0x00000001), %bb.17(0x7fffffff)
+  
+    %78:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %78.sub_8bit, %78.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.17, implicit killed $eflags
+    JMP_1 %bb.16
+  
+  bb.16.bb34:
+    successors: 
+  
+  
+  bb.17.bb35:
+    successors: %bb.18(0x7fffffff), %bb.19(0x00000001)
+  
+    TEST8rr %78.sub_8bit, %78.sub_8bit, implicit-def $eflags
+    JE_1 %bb.19, implicit killed $eflags
+  
+  bb.18:
+    %79:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
+    JMP_1 %bb.21
+  
+  bb.19.bb36:
+    successors: 
+  
+  
+  bb.20.bb38:
+    %78:gr32_abcd = COPY %0
+    %79:gr32 = COPY %0
+  
+  bb.21.bb40:
+    successors: %bb.22, %bb.23
+  
+    %35:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %35.sub_8bit, %35.sub_8bit, implicit-def $eflags
+    %80:gr32 = IMPLICIT_DEF
+    JNE_1 %bb.23, implicit killed $eflags
+    JMP_1 %bb.22
+  
+  bb.22.bb43:
+    ADJCALLSTACKDOWN32 0, 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
+    CALLpcrel32 @_Znwj, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp, implicit-def $eax
+    ADJCALLSTACKUP32 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
+    %80:gr32 = COPY killed $eax
+    MOV32mr undef %38:gr32, 1, $noreg, 0, $noreg, %78 :: (store 4 into `%18** undef`)
+    MOV32mr %79, 1, $noreg, 0, $noreg, %80 :: (store 4 into %ir.tmp46)
+    ADJCALLSTACKDOWN32 0, 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
+    CALLpcrel32 @_ZNSt3__127__tree_balance_after_insertIPNS_16__tree_node_baseIPvEEEEvT_S5_, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp
+    ADJCALLSTACKUP32 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
+  
+  bb.23.bb48:
+    successors: %bb.24(0x00000001), %bb.25(0x7fffffff)
+  
+    MOV32mi %80, 1, $noreg, 52, $noreg, @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private15_preEnd__authorEv :: (store 4 into %ir.tmp50)
+    %39:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %39.sub_8bit, %39.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.25, implicit killed $eflags
+    JMP_1 %bb.24
+  
+  bb.24.bb52:
+    successors: 
+  
+  
+  bb.25.bb53:
+    successors: %bb.27(0x7fffffff), %bb.26(0x00000001)
+  
+    %41:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %41.sub_8bit, %41.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.27, implicit killed $eflags
+    JMP_1 %bb.26
+  
+  bb.26.bb54:
+    successors: 
+  
+  
+  bb.27.bb55:
+    successors: %bb.29(0x7fffffff), %bb.28(0x00000001)
+  
+    %43:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %43.sub_8bit, %43.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.29, implicit killed $eflags
+    JMP_1 %bb.28
+  
+  bb.28.bb58:
+    successors: 
+  
+  
+  bb.29.bb59:
+    successors: %bb.31(0x7fffffff), %bb.30(0x00000001)
+  
+    %45:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %45.sub_8bit, %45.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.31, implicit killed $eflags
+    JMP_1 %bb.30
+  
+  bb.30.bb61:
+    successors: 
+  
+  
+  bb.31.bb62:
+    successors: %bb.32(0x00000001), %bb.33(0x7fffffff)
+  
+    %47:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %47.sub_8bit, %47.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.33, implicit killed $eflags
+    JMP_1 %bb.32
+  
+  bb.32.bb64:
+    successors: 
+  
+  
+  bb.33.bb65:
+    successors: %bb.37(0x30000000), %bb.34(0x50000000)
+  
+    %49:gr8 = MOV8ri 1
+    TEST8rr %49, %49, implicit-def $eflags
+    JNE_1 %bb.37, implicit killed $eflags
+    JMP_1 %bb.34
+  
+  bb.34.bb67:
+    successors: %bb.36(0x00000001), %bb.35(0x7fffffff)
+  
+    %81:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %81.sub_8bit, %81.sub_8bit, implicit-def $eflags
+    JE_1 %bb.36, implicit killed $eflags
+  
+  bb.35:
+    %82:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
+    JMP_1 %bb.38
+  
+  bb.36.bb70:
+    successors: 
+  
+  
+  bb.37.bb72:
+    %81:gr32_abcd = COPY %0
+    %82:gr32 = COPY %0
+  
+  bb.38.bb74:
+    successors: %bb.40(0x7fffffff), %bb.39(0x00000001)
+  
+    ADJCALLSTACKDOWN32 0, 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
+    CALLpcrel32 @_Znwj, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp, implicit-def $eax
+    ADJCALLSTACKUP32 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
+    %52:gr32 = COPY killed $eax
+    MOV32mr undef %53:gr32, 1, $noreg, 0, $noreg, %81 :: (store 4 into `%18** undef`)
+    MOV32mr %82, 1, $noreg, 0, $noreg, %52 :: (store 4 into %ir.tmp79)
+    ADJCALLSTACKDOWN32 0, 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
+    CALLpcrel32 @_ZNSt3__127__tree_balance_after_insertIPNS_16__tree_node_baseIPvEEEEvT_S5_, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp
+    ADJCALLSTACKUP32 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
+    MOV32mi %52, 1, $noreg, 36, $noreg, @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private14_end__commentsEv :: (store 4 into %ir.tmp81)
+    MOV32mr undef %54:gr32, 1, $noreg, 0, $noreg, %1 :: (store 4 into `%18** undef`)
+    %55:gr32 = MOV32rm %12, 1, $noreg, 140, $noreg :: (load 4 from %ir.3)
+    CMP32mi8 %55, 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (load 4 from %ir.tmp864)
+    JE_1 %bb.40, implicit killed $eflags
+    JMP_1 %bb.39
+  
+  bb.39.bb89:
+    successors: 
+  
+  
+  bb.40.bb90:
+    successors: %bb.42(0x00000001), %bb.41(0x7fffffff)
+  
+    %56:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %56.sub_8bit, %56.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.42, implicit killed $eflags
+    JMP_1 %bb.41
+  
+  bb.41.bb92:
+    successors: %bb.43(0x00000001), %bb.44(0x7fffffff)
+  
+    %58:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %58.sub_8bit, %58.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.43, implicit killed $eflags
+    JMP_1 %bb.44
+  
+  bb.42.bb94:
+    successors: 
+  
+  
+  bb.43.bb96:
+    successors: 
+  
+  
+  bb.44.bb97:
+    successors: %bb.45(0x00000001), %bb.46(0x7fffffff)
+  
+    %60:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %60.sub_8bit, %60.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.46, implicit killed $eflags
+    JMP_1 %bb.45
+  
+  bb.45.bb101:
+    successors: 
+  
+  
+  bb.46.bb102:
+    successors: %bb.48(0x7fffffff), %bb.47(0x00000001)
+  
+    %62:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %62.sub_8bit, %62.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.48, implicit killed $eflags
+    JMP_1 %bb.47
+  
+  bb.47.bb103:
+    successors: 
+  
+  
+  bb.48.bb104:
+    successors: %bb.50(0x7fffffff), %bb.49(0x00000001)
+  
+    %64:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %64.sub_8bit, %64.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.50, implicit killed $eflags
+    JMP_1 %bb.49
+  
+  bb.49.bb108:
+    successors: 
+  
+  
+  bb.50.bb109:
+    successors: %bb.51(0x00000001), %bb.52(0x7fffffff)
+  
+    %66:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %66.sub_8bit, %66.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.52, implicit killed $eflags
+    JMP_1 %bb.51
+  
+  bb.51.bb111:
+    successors: 
+  
+  
+  bb.52.bb112:
+    successors: %bb.54(0x7fffffff), %bb.53(0x00000001)
+  
+    %68:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %68.sub_8bit, %68.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.54, implicit killed $eflags
+    JMP_1 %bb.53
+  
+  bb.53.bb117:
+    successors: 
+  
+  
+  bb.54.bb118:
+    successors: %bb.55(0x00000001), %bb.56(0x7fffffff)
+  
+    %70:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %70.sub_8bit, %70.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.56, implicit killed $eflags
+    JMP_1 %bb.55
+  
+  bb.55.bb120:
+    successors: 
+  
+  
+  bb.56.bb121:
+    successors: %bb.57(0x00000001), %bb.58(0x7fffffff)
+  
+    %72:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %72.sub_8bit, %72.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.58, implicit killed $eflags
+    JMP_1 %bb.57
+  
+  bb.57.bb124:
+    successors: 
+  
+  
+  bb.58.bb125:
+    successors: %bb.62(0x00000001), %bb.59(0x7fffffff)
+  
+    CMP32mi8 %0, 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (load 4 from %ir.4)
+    JE_1 %bb.62, implicit killed $eflags
+    JMP_1 %bb.59
+  
+  bb.59.bb128:
+  
+  bb.60.bb129:
+    successors: %bb.60(0x7fffffff), %bb.61(0x00000001)
+  
+    CMP32ri undef %75:gr32, 95406325, implicit-def $eflags
+    JB_1 %bb.61, implicit killed $eflags
+    JMP_1 %bb.60
+  
+  bb.61.bb133:
+    successors: 
+  
+  
+  bb.62.bb135:
+    successors: %bb.63, %bb.64
+  
+    %76:gr32_abcd = MOV32r0 implicit-def dead $eflags
+    TEST8rr %76.sub_8bit, %76.sub_8bit, implicit-def $eflags
+    JNE_1 %bb.64, implicit killed $eflags
+    JMP_1 %bb.63
+  
+  bb.63.bb137:
+    successors: 
+  
+  
+  bb.64.bb138:
+
+...