Index: llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
===================================================================
--- llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -1213,7 +1213,7 @@
 class SWSP_MMR6_DESC
     : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
                       !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
-      MMR6Arch<"sw"> {
+      MMR6Arch<"swsp"> {
   let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
   let mayStore = 1;
 }
Index: llvm/lib/Target/Mips/MicroMipsInstrInfo.td
===================================================================
--- llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -654,7 +654,7 @@
                          LOAD_GP_FM_MM16<0x19>, ISA_MICROMIPS;
 def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
               LOAD_STORE_SP_FM_MM16<0x12>, ISA_MICROMIPS;
-def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
+def SWSP_MM : StoreSPMM16<"swsp", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
               LOAD_STORE_SP_FM_MM16<0x32>, ISA_MICROMIPS32_NOT_MIPS32R6;
 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16,
                    ISA_MICROMIPS;
@@ -1453,3 +1453,6 @@
 def : MipsInstAlias<"mthgc0 $rt, $rs",
                     (MTHGC0_MM COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
                     ISA_MICROMIPS32R5, ASE_VIRT;
+def : MipsInstAlias<"sw $rt, $offset",
+                    (SWSP_MM GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset), 1>,
+                    ISA_MICROMIPS;
Index: llvm/lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- llvm/lib/Target/Mips/MipsInstrInfo.td
+++ llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -2124,7 +2124,7 @@
             LW_FM<0x28>, ISA_MIPS1;
   def SH  : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>,
             ISA_MIPS1;
-  def SW  : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>, ISA_MIPS1;
+  def SW  : StdMMR6Rel, Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>, ISA_MIPS1;
 }
 
 /// load/store left/right
Index: llvm/test/CodeGen/Mips/micromips-sw.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Mips/micromips-sw.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+micromips \
+; RUN:     -filetype=obj -o - %s | llvm-objdump -d - \
+; RUN:   | FileCheck --check-prefix=MM2 %s
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs \
+; RUN:     -filetype=obj -o - %s | llvm-objdump -d - \
+; RUN:   | FileCheck --check-prefix=MM6 %s
+
+define void @fun(i32 %val) {
+; MM2-LABEL: fun:
+; MM2:         cb e5 sw $ra, 20($sp)
+
+; MM6-LABEL: fun:
+; MM6:         fb fd 00 14 sw $ra, 20($sp)
+entry:
+  call i32* @fun1()
+  ret void
+}
+
+declare i32* @fun1()