Index: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -245,6 +245,7 @@ class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>; class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>; class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>; +class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>; class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>; class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>; class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>; @@ -889,6 +890,8 @@ } class FMOV_S_MMR6_DESC : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>; +class FMOV_D_MMR6_DESC + : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>; class FNEG_S_MMR6_DESC : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>; @@ -1461,6 +1464,8 @@ ISA_MICROMIPS32R6; def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC, ISA_MICROMIPS32R6; +def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC, + ISA_MICROMIPS32R6; def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC, ISA_MICROMIPS32R6; def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6; Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td @@ -113,8 +113,7 @@ ISA_MICROMIPS, FGR_32 { string DecoderNamespace = "MicroMips"; } - // FIXME: This needs to be part of the instruction mapping tables. - def _D64_MM : ABSS_FT, + def _D64_MM : StdMMR6Rel, ABSS_FT, ISA_MICROMIPS, FGR_64 { string DecoderNamespace = "MicroMipsFP64"; } Index: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td @@ -142,7 +142,7 @@ SDPatternOperator OpNode= null_frag> { def _D32 : MMRel, ABSS_FT, FGR_32; - def _D64 : ABSS_FT, FGR_64 { + def _D64 : StdMMR6Rel, ABSS_FT, FGR_64 { string DecoderNamespace = "MipsFP64"; } } Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/fptosi.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/fptosi.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/fptosi.ll @@ -38,23 +38,23 @@ define i32 @test1(float %t) { ; M32-LABEL: test1: ; M32: # %bb.0: # %entry -; M32-NEXT: trunc.w.s $f0, $f12 # ; M32-NEXT: # > -; M32-NEXT: jr $ra # > -; M32-NEXT: mfc1 $2, $f0 # ; M32-NEXT: # > ; ; M32R2-FP64-LABEL: test1: ; M32R2-FP64: # %bb.0: # %entry -; M32R2-FP64-NEXT: trunc.w.s $f0, $f12 # ; M32R2-FP64-NEXT: # > -; M32R2-FP64-NEXT: jr $ra # > -; M32R2-FP64-NEXT: mfc1 $2, $f0 # ; M32R2-FP64-NEXT: # > ; @@ -66,23 +66,23 @@ ; M32R2-SF-NEXT: # > ; M32R2-SF-NEXT: .cfi_def_cfa_offset 24 ; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill -; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # > ; M32R2-SF-NEXT: .cfi_offset 31, -4 -; M32R2-SF-NEXT: jal __fixsfsi # > -; M32R2-SF-NEXT: nop # ; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # > ; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload -; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # > -; M32R2-SF-NEXT: jr $ra # > ; M32R2-SF-NEXT: addiu $sp, $sp, 24 # @@ -91,69 +91,69 @@ ; ; M32R3R5-LABEL: test1: ; M32R3R5: # %bb.0: # %entry -; M32R3R5-NEXT: trunc.w.s $f0, $f12 # ; M32R3R5-NEXT: # > -; M32R3R5-NEXT: jr $ra # > -; M32R3R5-NEXT: mfc1 $2, $f0 # ; M32R3R5-NEXT: # > ; ; M32R6-LABEL: test1: ; M32R6: # %bb.0: # %entry -; M32R6-NEXT: trunc.w.s $f0, $f12 # ; M32R6-NEXT: # > -; M32R6-NEXT: jr $ra # ; M32R6-NEXT: # > -; M32R6-NEXT: mfc1 $2, $f0 # ; M32R6-NEXT: # > ; ; M64-LABEL: test1: ; M64: # %bb.0: # %entry -; M64-NEXT: trunc.w.s $f0, $f12 # ; M64-NEXT: # > -; M64-NEXT: jr $ra # > -; M64-NEXT: mfc1 $2, $f0 # ; M64-NEXT: # > ; ; M64R6-LABEL: test1: ; M64R6: # %bb.0: # %entry -; M64R6-NEXT: trunc.w.s $f0, $f12 # ; M64R6-NEXT: # > -; M64R6-NEXT: jr $ra # ; M64R6-NEXT: # > -; M64R6-NEXT: mfc1 $2, $f0 # ; M64R6-NEXT: # > ; ; MMR2-FP32-LABEL: test1: ; MMR2-FP32: # %bb.0: # %entry -; MMR2-FP32-NEXT: trunc.w.s $f0, $f12 # ; MMR2-FP32-NEXT: # > -; MMR2-FP32-NEXT: jr $ra # > -; MMR2-FP32-NEXT: mfc1 $2, $f0 # ; MMR2-FP32-NEXT: # > ; ; MMR2-FP64-LABEL: test1: ; MMR2-FP64: # %bb.0: # %entry -; MMR2-FP64-NEXT: trunc.w.s $f0, $f12 # ; MMR2-FP64-NEXT: # > -; MMR2-FP64-NEXT: jr $ra # > -; MMR2-FP64-NEXT: mfc1 $2, $f0 # ; MMR2-FP64-NEXT: # > ; @@ -163,36 +163,36 @@ ; MMR2-SF-NEXT: # > ; MMR2-SF-NEXT: .cfi_def_cfa_offset 24 ; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill -; MMR2-SF-NEXT: # ; MMR2-SF-NEXT: # ; MMR2-SF-NEXT: # > ; MMR2-SF-NEXT: .cfi_offset 31, -4 -; MMR2-SF-NEXT: jal __fixsfsi # > -; MMR2-SF-NEXT: nop # ; MMR2-SF-NEXT: # ; MMR2-SF-NEXT: # > ; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload -; MMR2-SF-NEXT: # ; MMR2-SF-NEXT: # ; MMR2-SF-NEXT: # > ; MMR2-SF-NEXT: addiusp 24 # > -; MMR2-SF-NEXT: jrc $ra # > ; ; MMR6-LABEL: test1: ; MMR6: # %bb.0: # %entry -; MMR6-NEXT: trunc.w.s $f0, $f12 # ; MMR6-NEXT: # > -; MMR6-NEXT: mfc1 $2, $f0 # ; MMR6-NEXT: # > -; MMR6-NEXT: jrc $ra # > ; ; MMR6-SF-LABEL: test1: @@ -203,15 +203,15 @@ ; MMR6-SF-NEXT: # > ; MMR6-SF-NEXT: .cfi_def_cfa_offset 24 ; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill -; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > ; MMR6-SF-NEXT: .cfi_offset 31, -4 -; MMR6-SF-NEXT: jalr __fixsfsi # > ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload -; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > @@ -219,7 +219,7 @@ ; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > -; MMR6-SF-NEXT: jrc $ra # > entry: %conv = fptosi float %t to i32 @@ -229,23 +229,23 @@ define i32 @test2(double %t) { ; M32-LABEL: test2: ; M32: # %bb.0: # %entry -; M32-NEXT: trunc.w.d $f0, $f12 # ; M32-NEXT: # > -; M32-NEXT: jr $ra # > -; M32-NEXT: mfc1 $2, $f0 # ; M32-NEXT: # > ; ; M32R2-FP64-LABEL: test2: ; M32R2-FP64: # %bb.0: # %entry -; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 # ; M32R2-FP64-NEXT: # > -; M32R2-FP64-NEXT: jr $ra # > -; M32R2-FP64-NEXT: mfc1 $2, $f0 # ; M32R2-FP64-NEXT: # > ; @@ -257,23 +257,23 @@ ; M32R2-SF-NEXT: # > ; M32R2-SF-NEXT: .cfi_def_cfa_offset 24 ; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill -; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # > ; M32R2-SF-NEXT: .cfi_offset 31, -4 -; M32R2-SF-NEXT: jal __fixdfsi # > -; M32R2-SF-NEXT: nop # ; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # > ; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload -; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # > -; M32R2-SF-NEXT: jr $ra # > ; M32R2-SF-NEXT: addiu $sp, $sp, 24 # @@ -282,58 +282,58 @@ ; ; M32R3R5-LABEL: test2: ; M32R3R5: # %bb.0: # %entry -; M32R3R5-NEXT: trunc.w.d $f0, $f12 # ; M32R3R5-NEXT: # > -; M32R3R5-NEXT: jr $ra # > -; M32R3R5-NEXT: mfc1 $2, $f0 # ; M32R3R5-NEXT: # > ; ; M32R6-LABEL: test2: ; M32R6: # %bb.0: # %entry -; M32R6-NEXT: trunc.w.d $f0, $f12 # ; M32R6-NEXT: # > -; M32R6-NEXT: jr $ra # ; M32R6-NEXT: # > -; M32R6-NEXT: mfc1 $2, $f0 # ; M32R6-NEXT: # > ; ; M64-LABEL: test2: ; M64: # %bb.0: # %entry -; M64-NEXT: trunc.w.d $f0, $f12 # ; M64-NEXT: # > -; M64-NEXT: jr $ra # > -; M64-NEXT: mfc1 $2, $f0 # ; M64-NEXT: # > ; ; M64R6-LABEL: test2: ; M64R6: # %bb.0: # %entry -; M64R6-NEXT: trunc.w.d $f0, $f12 # ; M64R6-NEXT: # > -; M64R6-NEXT: jr $ra # ; M64R6-NEXT: # > -; M64R6-NEXT: mfc1 $2, $f0 # ; M64R6-NEXT: # > ; ; MMR2-FP32-LABEL: test2: ; MMR2-FP32: # %bb.0: # %entry -; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 # ; MMR2-FP32-NEXT: # > -; MMR2-FP32-NEXT: jr $ra # > -; MMR2-FP32-NEXT: mfc1 $2, $f0 # ; MMR2-FP32-NEXT: # > ; @@ -342,9 +342,9 @@ ; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 # ; MMR2-FP64-NEXT: # > -; MMR2-FP64-NEXT: jr $ra # > -; MMR2-FP64-NEXT: mfc1 $2, $f0 # ; MMR2-FP64-NEXT: # > ; @@ -354,36 +354,36 @@ ; MMR2-SF-NEXT: # > ; MMR2-SF-NEXT: .cfi_def_cfa_offset 24 ; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill -; MMR2-SF-NEXT: # ; MMR2-SF-NEXT: # ; MMR2-SF-NEXT: # > ; MMR2-SF-NEXT: .cfi_offset 31, -4 -; MMR2-SF-NEXT: jal __fixdfsi # > -; MMR2-SF-NEXT: nop # ; MMR2-SF-NEXT: # ; MMR2-SF-NEXT: # > ; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload -; MMR2-SF-NEXT: # ; MMR2-SF-NEXT: # ; MMR2-SF-NEXT: # > ; MMR2-SF-NEXT: addiusp 24 # > -; MMR2-SF-NEXT: jrc $ra # > ; ; MMR6-LABEL: test2: ; MMR6: # %bb.0: # %entry -; MMR6-NEXT: trunc.w.d $f0, $f12 # ; MMR6-NEXT: # > -; MMR6-NEXT: mfc1 $2, $f0 # ; MMR6-NEXT: # > -; MMR6-NEXT: jrc $ra # > ; ; MMR6-SF-LABEL: test2: @@ -394,15 +394,15 @@ ; MMR6-SF-NEXT: # > ; MMR6-SF-NEXT: .cfi_def_cfa_offset 24 ; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill -; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > ; MMR6-SF-NEXT: .cfi_offset 31, -4 -; MMR6-SF-NEXT: jalr __fixdfsi # > ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload -; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > @@ -410,7 +410,7 @@ ; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > -; MMR6-SF-NEXT: jrc $ra # > entry: %conv = fptosi double %t to i32 Index: llvm/trunk/test/CodeGen/Mips/micromips-mtc-mfc.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/micromips-mtc-mfc.ll +++ llvm/trunk/test/CodeGen/Mips/micromips-mtc-mfc.ll @@ -23,7 +23,7 @@ ; ; MM6-LABEL: foo: ; MM6: # %bb.0: # %entry -; MM6-NEXT: mov.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x06] +; MM6-NEXT: mov.d $f0, $f12 # encoding: [0x54,0x0c,0x20,0x7b] ; MM6-NEXT: mtc1 $zero, $f1 # encoding: [0x54,0x01,0x28,0x3b] ; MM6-NEXT: mthc1 $zero, $f1 # encoding: [0x54,0x01,0x38,0x3b] ; MM6-NEXT: cmp.ule.d $f1, $f12, $f1 # encoding: [0x54,0x2c,0x09,0xd5] Index: llvm/trunk/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll +++ llvm/trunk/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll @@ -7,51 +7,51 @@ define i64 @test(i32 signext %a, i32 signext %b) { ; MMR2-LABEL: test: ; MMR2: # %bb.0: # %entry -; MMR2-NEXT: li16 $2, 0 # ; MMR2-NEXT: # > -; MMR2-NEXT: li16 $3, 1 # ; MMR2-NEXT: # > -; MMR2-NEXT: mtlo $3 # > -; MMR2-NEXT: mthi $2 # > -; MMR2-NEXT: madd $4, $5 # ; MMR2-NEXT: # > -; MMR2-NEXT: mflo16 $2 # > -; MMR2-NEXT: mfhi16 $3 # > -; MMR2-NEXT: jrc $ra # > ; ; MMR2-DSP-LABEL: test: ; MMR2-DSP: # %bb.0: # %entry -; MMR2-DSP-NEXT: li16 $2, 0 # ; MMR2-DSP-NEXT: # > -; MMR2-DSP-NEXT: li16 $3, 1 # ; MMR2-DSP-NEXT: # > -; MMR2-DSP-NEXT: mtlo $3, $ac0 # ; MMR2-DSP-NEXT: # > -; MMR2-DSP-NEXT: mthi $2, $ac0 # ; MMR2-DSP-NEXT: # > -; MMR2-DSP-NEXT: madd $ac0, $4, $5 # ; MMR2-DSP-NEXT: # ; MMR2-DSP-NEXT: # ; MMR2-DSP-NEXT: # > -; MMR2-DSP-NEXT: mflo $2, $ac0 # ; MMR2-DSP-NEXT: # > -; MMR2-DSP-NEXT: jr $ra # > -; MMR2-DSP-NEXT: mfhi $3, $ac0 # ; MMR2-DSP-NEXT: # > entry: