Index: lib/Target/ARM/ARMInstrNEON.td =================================================================== --- lib/Target/ARM/ARMInstrNEON.td +++ lib/Target/ARM/ARMInstrNEON.td @@ -5133,9 +5133,10 @@ let Inst{2-0} = Vm{3-1}; } +// Vq, Vd, Vd[0-7], Idx[0-3] class VFMQ1 S> : N3VLaneCP8<0, S, 1, 1, (outs QPR:$Vd), - (ins DPR:$Vn, DPR:$Vm, VectorIndex16:$idx), + (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$idx), IIC_VMACD, opc, "f16", "$Vd, $Vn, $Vm$idx", "", []> { bits<2> idx; let Inst{5} = idx{1}; Index: test/MC/ARM/armv8a-fpmul-error.s =================================================================== --- test/MC/ARM/armv8a-fpmul-error.s +++ test/MC/ARM/armv8a-fpmul-error.s @@ -6,6 +6,8 @@ vfmal.f16 q0, d1, d2[4] VFMSL.F16 Q0, D1, D2[4] vfmal.f16 q0, d1, d2[-1] +VFMSL.F16 Q0, D1, D8[0] +vfmal.f16 q0, d1, d8[0] //CHECK-ERROR: error: invalid operand for instruction //CHECK-ERROR-NEXT: VFMAL.F16 D0, S1, S2[2] @@ -25,3 +27,21 @@ //CHECK-ERROR-NEXT: error: invalid operand for instruction //CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d2[-1] //CHECK-ERROR-NEXT: ^ +//CHECK-ERROR-NEXT: : error: invalid instruction, any one of the following would fix this: +//CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D8[0] +//CHECK-ERROR-NEXT: ^ +//CHECK-ERROR-NEXT: : note: operand must be a register in range [d0, d7] +//CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D8[0] +//CHECK-ERROR-NEXT: ^ +//CHECK-ERROR-NEXT: : note: too many operands for instruction +//CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D8[0] +//CHECK-ERROR-NEXT: ^ +//CHECK-ERROR-NEXT: : error: invalid instruction, any one of the following would fix this: +//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d8[0] +//CHECK-ERROR-NEXT: ^ +//CHECK-ERROR-NEXT: : note: operand must be a register in range [d0, d7] +//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d8[0] +//CHECK-ERROR-NEXT: ^ +//CHECK-ERROR-NEXT: 1: note: too many operands for instruction +//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d8[0] +//CHECK-ERROR-NEXT: ^