[mips] Some MIPS branch and likely instructions

[ipetkovic]

Summary

The patch adds support for the following MIPS branch and likely instructions:

• BGEZALL
• BGTZL
• BLEZL
• BLTZL

New patch version prevents usage of branch likely instructions for
microMIPS and adds corresponding disassembler test cases.

[vkalintiris]

lib/Target/Mips/MipsInstrInfo.td

1223–1233

Hi Igor, I added support for the branch likely instructions last week (see D5782 and D5802).
However, I didn't consider what happens in MicroMips mode as I don't know enough about it.

[dsanders]

lib/Target/Mips/MipsInstrInfo.td

1223–1233

Vasileios: Just for future reference, it's preferable to reference the committed revision wherever possible (r220036, and r220042 in this case).

[ipetkovic]

New patch version prevents usage of branch likely instructions for
microMIPS and adds corresponding disassembler test cases.

[dsanders]

NotInMicroMips doesn't belong in InsnPredicates (and therefore does not belong in the ISA_* classes). It should be in the AdditionalPredicates list. The reason for this is that microMIPS is (almost) an alternate encoding rather than an alternate ISA. It accepts the same assembly instructions (although some become macros and this is what NotInMicroMips is currently handling). Eventually microMIPS will be represented properly in EncodingPredicates with predicates for standard/microMIPS/both encodings.

[ipetkovic]

NotInMicroMips defined in a AdditionalPredicates list for branch and likely instructions that are not featured in microMIPS.

[dsanders]

Thanks. LGTM

[seanbruno]

This looks to have been committed in one form or another. Can we close this review?

lib/Target/Mips/MipsInstrInfo.td

 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
 }
 
 /// Jump and Branch Instructions
 def J       : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
               AdditionalRequires<[RelocStatic]>, IsBranch;
 def JR      : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
 def BEQ     : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
-def BEQL    : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
-              BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
 def BNE     : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
-def BNEL    : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
-              BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
 def BGEZ    : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
               BGEZ_FM<1, 1>;
-def BGEZL   : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
-              BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
 def BGTZ    : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
               BGEZ_FM<7, 0>;
-def BGTZL   : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
-              BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
 def BLEZ    : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
               BGEZ_FM<6, 0>;
-def BLEZL   : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
-              BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
 def BLTZ    : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
               BGEZ_FM<1, 0>;
-def BLTZL   : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
-              BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
 def B       : UncondBranch<BEQ>;
 
 def JAL  : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
-let AdditionalPredicates = [NotInMicroMips] in {
-  def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
-  def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
-}
 
 // FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32.
 def JALX  : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6;
 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
              ISA_MIPS1_NOT_32R6_64R6;
-def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
-              BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
              ISA_MIPS1_NOT_32R6_64R6;
-def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
-              BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
 def TAILCALL : TailCall<J>;
 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
 
+//Jump and Branch Instructions not featured in microMIPS
+let AdditionalPredicates = [NotInMicroMips] in {
+  
+  def BEQL    : CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
+              BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
+  def BNEL    : CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
+              BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
+  def BGEZL   : CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
+              BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
+  def BGTZL   : CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
+              BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
+  def BLEZL   : CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
+              BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
+  def BLTZL   : CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
+              BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
+
+  def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
+  def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
+  
+  def BGEZALL : BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
+              BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
+  def BLTZALL : BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
+              BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
+}
+
 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
 class PseudoIndirectBranchBase<RegisterOperand RO> :
     MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], IIBranch> {
   let isTerminator=1;
   let isBarrier=1;
   let hasDelaySlot = 1;
   let isBranch = 1;

test/MC/Disassembler/Mips/mips32.txt

 0x45 0x01 0x01 0x4d
 
 # CHECK: bc1t $fcc7, 1332
 0x45 0x1d 0x01 0x4d
 
 # CHECK: beq $9, $6, 1332
 0x11 0x26 0x01 0x4d
 
+# CHECK: beql $9, $6, 1332
+0x51 0x26 0x01 0x4d
+
 # CHECK: bgez  $6, 1332
 0x04 0xc1 0x01 0x4d
 
+# CHECK: bgezl  $6, 1332
+0x04 0xc3 0x01 0x4d
+
 # CHECK: bgezal  $6, 1332
 0x04 0xd1 0x01 0x4d
 
+# CHECK: bgezall $6, 1332
+0x04 0xd3 0x01 0x4d
+
 # CHECK: bgtz  $6, 1332
 0x1c 0xc0 0x01 0x4d
 
+# CHECK: bgtzl  $6, 1332
+0x5c 0xc0 0x01 0x4d
+
 # CHECK: blez  $6, 1332
 0x18 0xc0 0x01 0x4d
 
+# CHECK: blezl  $6, 1332
+0x58 0xc0 0x01 0x4d
+
+# CHECK: bltzl  $6, 1332
+0x04 0xc2 0x01 0x4d
+
+# CHECK: bltzall  $6, 1332
+0x04 0xd2 0x01 0x4d
+
 # CHECK: bne $9, $6, 1332
 0x15 0x26 0x01 0x4d
 
+# CHECK: bnel $9, $6, 1332
+0x55 0x26 0x01 0x4d
+
 # CHECK: c.eq.d $f12, $f14
 0x46 0x2e 0x60 0x32
 
 # CHECK: c.eq.s $f6, $f7
 0x46 0x07 0x30 0x32
 
 # CHECK: c.f.d $f12, $f14
 0x46 0x2e 0x60 0x30

test/MC/Disassembler/Mips/mips32_le.txt

 0x4d 0x01 0x01 0x45
 
 # CHECK: bc1t $fcc7, 1332
 0x4d 0x01 0x1d 0x45
 
 # CHECK: beq $9, $6, 1332
 0x4d 0x01 0x26 0x11
 
+# CHECK: beql $9, $6, 1332
+0x4d 0x01 0x26 0x51
+
 # CHECK: bgez  $6, 1332
 0x4d 0x01 0xc1 0x04
 
+# CHECK: bgezl  $6, 1332
+0x4d 0x01 0xc3 0x04
+
 # CHECK: bgezal  $6, 1332
 0x4d 0x01 0xd1 0x04
 
+# CHECK: bgezall $6, 1332
+0x4d 0x01 0xd3  0x04
+
 # CHECK: bgtz  $6, 1332
 0x4d 0x01 0xc0 0x1c
 
+# CHECK: bgtzl  $6, 1332
+0x4d  0x01  0xc0 0x5c
+
 # CHECK: blez  $6, 1332
 0x4d 0x01 0xc0 0x18
 
+# CHECK: blezl  $6, 1332
+0x4d 0x01 0xc0 0x58
+
+# CHECK: bltzl  $6, 1332
+0x4d 0x01 0xc2 0x04
+
+# CHECK: bltzall  $6, 1332
+0x4d 0x01 0xd2 0x04
+
 # CHECK: bne $9, $6, 1332
 0x4d 0x01 0x26 0x15
 
+# CHECK: bnel $9, $6, 1332
+0x4d 0x01 0x26 0x55
+
 # CHECK: c.eq.d $f12, $f14
 0x32 0x60 0x2e 0x46
 
 # CHECK: c.eq.s $f6, $f7
 0x32 0x30 0x07 0x46
 
 # CHECK: c.f.d $f12, $f14
 0x30 0x60 0x2e 0x46