Index: lib/Target/RISCV/RISCVISelLowering.h
===================================================================
--- lib/Target/RISCV/RISCVISelLowering.h
+++ lib/Target/RISCV/RISCVISelLowering.h
@@ -106,6 +106,10 @@
   Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
                                  AtomicOrdering Ord) const override;
 
+  ISD::NodeType getExtendForAtomicOps() const override {
+    return ISD::SIGN_EXTEND;
+  }
+
 private:
   void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
                         const SmallVectorImpl<ISD::InputArg> &Ins,
Index: test/CodeGen/RISCV/atomic-cmpxchg-flag.ll
===================================================================
--- /dev/null
+++ test/CodeGen/RISCV/atomic-cmpxchg-flag.ll
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64IA %s
+
+define i1 @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 signext %cmp, i32 signext %val) {
+; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
+; RV64IA:       lr.w.aqrl [[OLD:[ast][0-9]+]]
+; RV64IA:       bne [[OLD]], [[CMP:a[0-7]+]], {{.*}}
+; RV64IA-NOT:   [[CMP]]
+; RV64IA:       xor {{.*}} [[OLD]], [[CMP]]
+entry:
+  %0 = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst
+  %1 = extractvalue { i32, i1 } %0, 1
+  ret i1 %1
+}