[ARM] Fix selection of VLDR.16 instruction with imm offset

[olista01]

Summary

The isScaledConstantInRange function takes upper and lower bounds which are checked after dividing by the scale, so the bounds checks for half, single and double precision should all be the same. Previously, we had wrong bounds checks for half precision, so selected an immediate the instructions can't actually represent.

[efriedma]

LGTM

llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp

bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
                              SDValue &Offset, SDValue &Opc);
   bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
                              SDValue &Offset, SDValue &Opc);
   bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
   bool SelectAddrMode3(SDValue N, SDValue &Base,
                        SDValue &Offset, SDValue &Opc);
   bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
                              SDValue &Offset, SDValue &Opc);
-  bool IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset,
-                         int Lwb, int Upb, bool FP16);
+  bool IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset, bool FP16);
   bool SelectAddrMode5(SDValue N, SDValue &Base, SDValue &Offset);
   bool SelectAddrMode5FP16(SDValue N, SDValue &Base, SDValue &Offset);
   bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
   bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
 
   bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
 
   // Thumb Addressing Modes:
bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
 
   Offset = N;
   Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), SDLoc(Op),
                                   MVT::i32);
   return true;
 }
 
 bool ARMDAGToDAGISel::IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset,
-                                        int Lwb, int Upb, bool FP16) {
+                                        bool FP16) {
   if (!CurDAG->isBaseWithConstantOffset(N)) {
     Base = N;
     if (N.getOpcode() == ISD::FrameIndex) {
       int FI = cast<FrameIndexSDNode>(N)->getIndex();
       Base = CurDAG->getTargetFrameIndex(
           FI, TLI->getPointerTy(CurDAG->getDataLayout()));
     } else if (N.getOpcode() == ARMISD::Wrapper &&
                N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
                N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
                N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
       Base = N.getOperand(0);
     }
     Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
                                        SDLoc(N), MVT::i32);
     return true;
   }
 
   // If the RHS is +/- imm8, fold into addr mode.
   int RHSC;
   const int Scale = FP16 ? 2 : 4;
 
-  if (isScaledConstantInRange(N.getOperand(1), Scale, Lwb, Upb, RHSC)) {
+  if (isScaledConstantInRange(N.getOperand(1), Scale, -255, 256, RHSC)) {
     Base = N.getOperand(0);
     if (Base.getOpcode() == ISD::FrameIndex) {
       int FI = cast<FrameIndexSDNode>(Base)->getIndex();
       Base = CurDAG->getTargetFrameIndex(
           FI, TLI->getPointerTy(CurDAG->getDataLayout()));
     }
 
     ARM_AM::AddrOpc AddSub = ARM_AM::add;
else
     Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
                                        SDLoc(N), MVT::i32);
 
   return true;
 }
 
 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
                                       SDValue &Base, SDValue &Offset) {
-  int Lwb = -256 + 1;
-  int Upb = 256;
-  return IsAddressingMode5(N, Base, Offset, Lwb, Upb, /*FP16=*/ false);
+  return IsAddressingMode5(N, Base, Offset, /*FP16=*/ false);
 }
 
 bool ARMDAGToDAGISel::SelectAddrMode5FP16(SDValue N,
                                           SDValue &Base, SDValue &Offset) {
-  int Lwb = -512 + 1;
-  int Upb = 512;
-  return IsAddressingMode5(N, Base, Offset, Lwb, Upb, /*FP16=*/ true);
+  return IsAddressingMode5(N, Base, Offset, /*FP16=*/ true);
 }
 
 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
                                       SDValue &Align) {
   Addr = N;
 
   unsigned Alignment = 0;
 

llvm/trunk/test/CodeGen/ARM/fp16-load-store.ll

+; RUN: llc < %s -mtriple armv8a--none-eabi -mattr=+fullfp16 | FileCheck %s
+
+define void @load_zero(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: load_zero:
+; CHECK: vldr.16 {{s[0-9]+}}, [r0]
+  %arrayidx = getelementptr inbounds half, half* %in, i32 0
+  %load = load half, half* %arrayidx, align 2
+  store half %load, half* %out
+  ret void
+}
+
+define void @load_255(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: load_255:
+; CHECK: vldr.16 {{s[0-9]+}}, [r0, #510]
+  %arrayidx = getelementptr inbounds half, half* %in, i32 255
+  %load = load half, half* %arrayidx, align 2
+  store half %load, half* %out
+  ret void
+}
+
+define void @load_256(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: load_256:
+; CHECK: add     [[ADDR:r[0-9]+]], r0, #512
+; CHECK: vldr.16 {{s[0-9]+}}, {{\[}}[[ADDR]]{{\]}}
+  %arrayidx = getelementptr inbounds half, half* %in, i32 256
+  %load = load half, half* %arrayidx, align 2
+  store half %load, half* %out
+  ret void
+}
+
+define void @load_neg_255(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: load_neg_255:
+; CHECK: vldr.16 {{s[0-9]+}}, [r0, #-510]
+  %arrayidx = getelementptr inbounds half, half* %in, i32 -255
+  %load = load half, half* %arrayidx, align 2
+  store half %load, half* %out
+  ret void
+}
+
+define void @load_neg_256(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: load_neg_256:
+; CHECK: sub     [[ADDR:r[0-9]+]], r0, #512
+; CHECK: vldr.16 {{s[0-9]+}}, {{\[}}[[ADDR]]{{\]}}
+  %arrayidx = getelementptr inbounds half, half* %in, i32 -256
+  %load = load half, half* %arrayidx, align 2
+  store half %load, half* %out
+  ret void
+}
+
+define void @store_zero(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: store_zero:
+  %load = load half, half* %in, align 2
+; CHECK: vstr.16 {{s[0-9]+}}, [r1]
+  %arrayidx = getelementptr inbounds half, half* %out, i32 0
+  store half %load, half* %arrayidx
+  ret void
+}
+
+define void @store_255(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: store_255:
+  %load = load half, half* %in, align 2
+; CHECK: vstr.16 {{s[0-9]+}}, [r1, #510]
+  %arrayidx = getelementptr inbounds half, half* %out, i32 255
+  store half %load, half* %arrayidx
+  ret void
+}
+
+define void @store_256(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: store_256:
+  %load = load half, half* %in, align 2
+; CHECK: add     [[ADDR:r[0-9]+]], r1, #512
+; CHECK: vstr.16 {{s[0-9]+}}, {{\[}}[[ADDR]]{{\]}}
+  %arrayidx = getelementptr inbounds half, half* %out, i32 256
+  store half %load, half* %arrayidx
+  ret void
+}
+
+define void @store_neg_255(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: store_neg_255:
+  %load = load half, half* %in, align 2
+; CHECK: vstr.16 {{s[0-9]+}}, [r1, #-510]
+  %arrayidx = getelementptr inbounds half, half* %out, i32 -255
+  store half %load, half* %arrayidx
+  ret void
+}
+
+define void @store_neg_256(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: store_neg_256:
+  %load = load half, half* %in, align 2
+; CHECK: sub     [[ADDR:r[0-9]+]], r1, #512
+; CHECK: vstr.16 {{s[0-9]+}}, {{\[}}[[ADDR]]{{\]}}
+  %arrayidx = getelementptr inbounds half, half* %out, i32 -256
+  store half %load, half* %arrayidx
+  ret void
+}