Index: lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrInfo.td +++ lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -1039,7 +1039,7 @@ class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>; class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd, - AFGR64Opnd, II_TRUNC>; + FGR64Opnd, II_TRUNC>; class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>; class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd, @@ -1749,6 +1749,8 @@ def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1_MMR6 ZERO))>, ISA_MICROMIPS32R6; def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), (TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6; +def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), + (TRUNC_W_S_MMR6 FGR32Opnd:$src)>, ISA_MICROMIPS32R6; def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm), (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>, Index: lib/Target/Mips/MicroMipsInstrFPU.td =================================================================== --- lib/Target/Mips/MicroMipsInstrFPU.td +++ lib/Target/Mips/MicroMipsInstrFPU.td @@ -424,6 +424,15 @@ def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), (TRUNC_W_MM AFGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; +def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), + (CVT_W_D64_MM FGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6, + FGR_64; +def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), + (TRUNC_W_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6, + FGR_32; +def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), + (TRUNC_W_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6, + FGR_64; // Selects defm : MovzPats0, Index: test/CodeGen/Mips/llvm-ir/fptosi.ll =================================================================== --- /dev/null +++ test/CodeGen/Mips/llvm-ir/fptosi.ll @@ -0,0 +1,249 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -asm-show-inst | FileCheck %s -check-prefixes=ALL,NOT-MM,M32,M32-NOTFP64,M32D +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -asm-show-inst | FileCheck %s -check-prefixes=ALL,NOT-MM,M32,M32-NOTFP64,M32R2 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst | FileCheck %s -check-prefixes=ALL,NOT-MM,M32,M32R2-FP64 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+soft-float -asm-show-inst | FileCheck %s -check-prefixes=ALL,SF,M32R2-SF +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -asm-show-inst | FileCheck %s -check-prefixes=ALL,NOT-MM,M32,M32-NOTFP64,M32R3 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r5 -asm-show-inst | FileCheck %s -check-prefixes=ALL,NOT-MM,M32,M32-NOTFP64,M32R5 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -asm-show-inst | FileCheck %s -check-prefixes=ALL,NOT-MM,M32R6 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips3 -asm-show-inst | FileCheck %s -check-prefixes=ALL,NOT-MM,M64,M3 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64 -asm-show-inst | FileCheck %s -check-prefixes=ALL,NOT-MM,M64,M64D +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r2 -asm-show-inst | FileCheck %s -check-prefixes=ALL,NOT-MM,M64,M64R2 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r6 -asm-show-inst | FileCheck %s -check-prefixes=ALL,NOT-MM,M64R6 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips -asm-show-inst | FileCheck %s -check-prefixes=ALL,MM,MMR2,MMR2-FP32 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,fp64 -asm-show-inst | FileCheck %s -check-prefixes=ALL,MM,MMR2,MMR2-FP64 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips -asm-show-inst | FileCheck %s -check-prefixes=ALL,MM,MMR6,MMR6-FP32 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips,fp64 -asm-show-inst | FileCheck %s -check-prefixes=ALL,MM,MMR6,MMR6-FP64 + +; Test that fptosi can be matched for MIPS targets for various FPU +; configurations + +define i32 @test1(float %t) { +; M32-LABEL: test1: +; M32: # %bb.0: # %entry +; M32-NEXT: trunc.w.s $f0, $f12 # +; M32-NEXT: # > +; M32-NEXT: jr $ra # > +; M32-NEXT: mfc1 $2, $f0 # +; M32-NEXT: # > +; +; SF-LABEL: test1: +; SF: # %bb.0: # %entry +; SF-NEXT: addiu $sp, $sp, -24 # +; SF-NEXT: # +; SF-NEXT: # > +; SF-NEXT: .cfi_def_cfa_offset 24 +; SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill +; SF-NEXT: # +; SF-NEXT: # +; SF-NEXT: # > +; SF-NEXT: .cfi_offset 31, -4 +; SF-NEXT: jal __fixsfsi # > +; SF-NEXT: nop # +; SF-NEXT: # +; SF-NEXT: # > +; SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload +; SF-NEXT: # +; SF-NEXT: # +; SF-NEXT: # > +; SF-NEXT: jr $ra # > +; SF-NEXT: addiu $sp, $sp, 24 # +; SF-NEXT: # +; SF-NEXT: # > +; +; M32R6-LABEL: test1: +; M32R6: # %bb.0: # %entry +; M32R6-NEXT: trunc.w.s $f0, $f12 # +; M32R6-NEXT: # > +; M32R6-NEXT: jr $ra # +; M32R6-NEXT: # > +; M32R6-NEXT: mfc1 $2, $f0 # +; M32R6-NEXT: # > +; +; M64-LABEL: test1: +; M64: # %bb.0: # %entry +; M64-NEXT: trunc.w.s $f0, $f12 # +; M64-NEXT: # > +; M64-NEXT: jr $ra # > +; M64-NEXT: mfc1 $2, $f0 # +; M64-NEXT: # > +; +; M64R6-LABEL: test1: +; M64R6: # %bb.0: # %entry +; M64R6-NEXT: trunc.w.s $f0, $f12 # +; M64R6-NEXT: # > +; M64R6-NEXT: jr $ra # +; M64R6-NEXT: # > +; M64R6-NEXT: mfc1 $2, $f0 # +; M64R6-NEXT: # > +; +; MMR2-LABEL: test1: +; MMR2: # %bb.0: # %entry +; MMR2-NEXT: trunc.w.s $f0, $f12 # +; MMR2-NEXT: # > +; MMR2-NEXT: jr $ra # > +; MMR2-NEXT: mfc1 $2, $f0 # +; MMR2-NEXT: # > +; +; MMR6-LABEL: test1: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: trunc.w.s $f0, $f12 # +; MMR6-NEXT: # > +; MMR6-NEXT: mfc1 $2, $f0 # +; MMR6-NEXT: # > +; MMR6-NEXT: jrc $ra # > +entry: + %conv = fptosi float %t to i32 + ret i32 %conv +} + +define i32 @test2(double %t) { +; M32-NOTFP64-LABEL: test2: +; M32-NOTFP64: # %bb.0: # %entry +; M32-NOTFP64-NEXT: trunc.w.d $f0, $f12 # +; M32-NOTFP64-NEXT: # > +; M32-NOTFP64-NEXT: jr $ra # > +; M32-NOTFP64-NEXT: mfc1 $2, $f0 # +; M32-NOTFP64-NEXT: # > +; +; M32R2-FP64-LABEL: test2: +; M32R2-FP64: # %bb.0: # %entry +; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 # +; M32R2-FP64-NEXT: # > +; M32R2-FP64-NEXT: jr $ra # > +; M32R2-FP64-NEXT: mfc1 $2, $f0 # +; M32R2-FP64-NEXT: # > +; +; SF-LABEL: test2: +; SF: # %bb.0: # %entry +; SF-NEXT: addiu $sp, $sp, -24 # +; SF-NEXT: # +; SF-NEXT: # > +; SF-NEXT: .cfi_def_cfa_offset 24 +; SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill +; SF-NEXT: # +; SF-NEXT: # +; SF-NEXT: # > +; SF-NEXT: .cfi_offset 31, -4 +; SF-NEXT: jal __fixdfsi # > +; SF-NEXT: nop # +; SF-NEXT: # +; SF-NEXT: # > +; SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload +; SF-NEXT: # +; SF-NEXT: # +; SF-NEXT: # > +; SF-NEXT: jr $ra # > +; SF-NEXT: addiu $sp, $sp, 24 # +; SF-NEXT: # +; SF-NEXT: # > +; +; M32R6-LABEL: test2: +; M32R6: # %bb.0: # %entry +; M32R6-NEXT: trunc.w.d $f0, $f12 # +; M32R6-NEXT: # > +; M32R6-NEXT: jr $ra # +; M32R6-NEXT: # > +; M32R6-NEXT: mfc1 $2, $f0 # +; M32R6-NEXT: # > +; +; M64-LABEL: test2: +; M64: # %bb.0: # %entry +; M64-NEXT: trunc.w.d $f0, $f12 # +; M64-NEXT: # > +; M64-NEXT: jr $ra # > +; M64-NEXT: mfc1 $2, $f0 # +; M64-NEXT: # > +; +; M64R6-LABEL: test2: +; M64R6: # %bb.0: # %entry +; M64R6-NEXT: trunc.w.d $f0, $f12 # +; M64R6-NEXT: # > +; M64R6-NEXT: jr $ra # +; M64R6-NEXT: # > +; M64R6-NEXT: mfc1 $2, $f0 # +; M64R6-NEXT: # > +; +; MMR2-FP32-LABEL: test2: +; MMR2-FP32: # %bb.0: # %entry +; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 # +; MMR2-FP32-NEXT: # > +; MMR2-FP32-NEXT: jr $ra # > +; MMR2-FP32-NEXT: mfc1 $2, $f0 # +; MMR2-FP32-NEXT: # > +; +; MMR2-FP64-LABEL: test2: +; MMR2-FP64: # %bb.0: # %entry +; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 # +; MMR2-FP64-NEXT: # > +; MMR2-FP64-NEXT: jr $ra # > +; MMR2-FP64-NEXT: mfc1 $2, $f0 # +; MMR2-FP64-NEXT: # > +; +; MMR6-LABEL: test2: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: trunc.w.d $f0, $f12 # +; MMR6-NEXT: # > +; MMR6-NEXT: mfc1 $2, $f0 # +; MMR6-NEXT: # > +; MMR6-NEXT: jrc $ra # > +entry: + %conv = fptosi double %t to i32 + ret i32 %conv +}