Index: lib/Target/Mips/MicroMipsInstrFPU.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrFPU.td
+++ lib/Target/Mips/MicroMipsInstrFPU.td
@@ -424,6 +424,9 @@
 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
               (TRUNC_W_MM AFGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6,
               FGR_32;
+def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
+              (TRUNC_W_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6,
+              FGR_32;
 
 // Selects
 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>,
Index: test/CodeGen/Mips/trunc-w-s-mm.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/trunc-w-s-mm.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mipsel-linux-gnu -mattr=+micromips -relocation-model=pic < %s | FileCheck %s
+
+; Test that should fail if there is no DAGISel pattern for TruncIntFP to
+; to TRUNC_W_S_MM
+
+define i32 @test(float %t) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addiu $sp, $sp, -8
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    swc1 $f12, 4($sp)
+; CHECK-NEXT:    trunc.w.s $f0, $f12
+; CHECK-NEXT:    mfc1 $2, $f0
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    addiu $sp, $sp, 8
+entry:
+  %t.addr = alloca float, align 4
+  store float %t, float* %t.addr, align 4
+  %0 = load float, float* %t.addr, align 4
+  %conv = fptosi float %0 to i32
+  ret i32 %conv
+}