Index: llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp +++ llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp @@ -139,6 +139,26 @@ using namespace TargetOpcode; switch (I.getOpcode()) { + case G_UMULH: { + unsigned PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass); + MachineInstr *PseudoMULTu, *PseudoMove; + + PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu)) + .addDef(PseudoMULTuReg) + .add(I.getOperand(1)) + .add(I.getOperand(2)); + if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI)) + return false; + + PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI)) + .addDef(I.getOperand(0).getReg()) + .addUse(PseudoMULTuReg); + if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI)) + return false; + + I.eraseFromParent(); + return true; + } case G_GEP: { MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) .add(I.getOperand(0)) Index: llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp +++ llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -32,9 +32,12 @@ .legalFor({s32}) .minScalar(0, s32); - getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE}) + getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO}) .lowerFor({{s32, s1}}); + getActionDefinitionsBuilder(G_UMULH) + .legalFor({s32}); + getActionDefinitionsBuilder({G_LOAD, G_STORE}) .legalForTypesWithMemDesc({{s32, p0, 8, 8}, {s32, p0, 16, 8}, Index: llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp +++ llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp @@ -86,6 +86,7 @@ case G_ADD: case G_SUB: case G_MUL: + case G_UMULH: case G_LOAD: case G_STORE: case G_ZEXTLOAD: Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir =================================================================== --- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir @@ -3,6 +3,7 @@ --- | define void @mul_i32(i32 %x, i32 %y) {entry: ret void} + define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void } ... --- @@ -29,3 +30,42 @@ RetRA implicit $v0 ... +--- +name: umul_with_overflow +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $a0, $a1, $a2 + + ; MIPS32-LABEL: name: umul_with_overflow + ; MIPS32: liveins: $a0, $a1, $a2 + ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 + ; MIPS32: [[PseudoMULTu:%[0-9]+]]:acc64 = PseudoMULTu [[COPY]], [[COPY1]] + ; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoMULTu]] + ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0 + ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 0 + ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[PseudoMFHI]], [[ORi]] + ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[XOR]] + ; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi 0 + ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi [[LUi1]], 1 + ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi1]] + ; MIPS32: SB [[AND]], [[COPY2]], 0 :: (store 1 into %ir.pcarry_flag) + ; MIPS32: RetRA + %0:gprb(s32) = COPY $a0 + %1:gprb(s32) = COPY $a1 + %2:gprb(p0) = COPY $a2 + %6:gprb(s32) = G_UMULH %0, %1 + %7:gprb(s32) = G_CONSTANT i32 0 + %8:gprb(s32) = G_ICMP intpred(ne), %6(s32), %7 + %9:gprb(s32) = G_CONSTANT i32 1 + %10:gprb(s32) = COPY %8(s32) + %5:gprb(s32) = G_AND %10, %9 + G_STORE %5(s32), %2(p0) :: (store 1 into %ir.pcarry_flag) + RetRA + +... Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir =================================================================== --- llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir @@ -9,6 +9,7 @@ define void @mul_i16_sext() {entry: ret void} define void @mul_i16_zext() {entry: ret void} define void @mul_i16_aext() {entry: ret void} + define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void } ... --- @@ -211,3 +212,32 @@ RetRA implicit $v0 ... +--- +name: umul_with_overflow +alignment: 2 +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $a0, $a1, $a2 + + ; MIPS32-LABEL: name: umul_with_overflow + ; MIPS32: liveins: $a0, $a1, $a2 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2 + ; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[COPY1]] + ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]] + ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] + ; MIPS32: G_STORE [[AND]](s32), [[COPY2]](p0) :: (store 1 into %ir.pcarry_flag) + ; MIPS32: RetRA + %0:_(s32) = COPY $a0 + %1:_(s32) = COPY $a1 + %2:_(p0) = COPY $a2 + %3:_(s32), %4:_(s1) = G_UMULO %0, %1 + G_STORE %4(s1), %2(p0) :: (store 1 into %ir.pcarry_flag) + RetRA + +... Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll @@ -86,3 +86,25 @@ %mul = mul i16 %b, %a ret i16 %mul } + +declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32) +define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { +; MIPS32-LABEL: umul_with_overflow: +; MIPS32: # %bb.0: +; MIPS32-NEXT: multu $4, $5 +; MIPS32-NEXT: mfhi $4 +; MIPS32-NEXT: lui $5, 0 +; MIPS32-NEXT: ori $5, $5, 0 +; MIPS32-NEXT: xor $4, $4, $5 +; MIPS32-NEXT: sltu $4, $zero, $4 +; MIPS32-NEXT: lui $5, 0 +; MIPS32-NEXT: ori $5, $5, 1 +; MIPS32-NEXT: and $4, $4, $5 +; MIPS32-NEXT: sb $4, 0($6) +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop + %res = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %lhs, i32 %rhs) + %carry_flag = extractvalue { i32, i1 } %res, 1 + store i1 %carry_flag, i1* %pcarry_flag + ret void +} Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir =================================================================== --- llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir @@ -3,6 +3,7 @@ --- | define void @mul_i32(i32 %x, i32 %y) {entry: ret void} + define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void } ... --- @@ -28,3 +29,38 @@ RetRA implicit $v0 ... +--- +name: umul_with_overflow +alignment: 2 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $a0, $a1, $a2 + + ; MIPS32-LABEL: name: umul_with_overflow + ; MIPS32: liveins: $a0, $a1, $a2 + ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2 + ; MIPS32: [[UMULH:%[0-9]+]]:gprb(s32) = G_UMULH [[COPY]], [[COPY1]] + ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]] + ; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32) + ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C1]] + ; MIPS32: G_STORE [[AND]](s32), [[COPY2]](p0) :: (store 1 into %ir.pcarry_flag) + ; MIPS32: RetRA + %0:_(s32) = COPY $a0 + %1:_(s32) = COPY $a1 + %2:_(p0) = COPY $a2 + %6:_(s32) = G_UMULH %0, %1 + %7:_(s32) = G_CONSTANT i32 0 + %8:_(s32) = G_ICMP intpred(ne), %6(s32), %7 + %9:_(s32) = G_CONSTANT i32 1 + %10:_(s32) = COPY %8(s32) + %5:_(s32) = G_AND %10, %9 + G_STORE %5(s32), %2(p0) :: (store 1 into %ir.pcarry_flag) + RetRA + +...