Index: llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td +++ llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td @@ -821,7 +821,9 @@ def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; -let isCodeGenOnly = 1 in { +let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, + isReMaterializable = 1 in { + def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), "vxor $vD, $vD, $vD", IIC_VecFP, [(set v16i8:$vD, (v16i8 immAllZerosV))]>; Index: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -332,6 +332,15 @@ case PPC::ADDIStocHA: case PPC::ADDItocL: case PPC::LOAD_STACK_GUARD: + case PPC::XXLXORz: + case PPC::XXLXORspz: + case PPC::XXLXORdpz: + case PPC::V_SET0B: + case PPC::V_SET0H: + case PPC::V_SET0: + case PPC::V_SETALLONESB: + case PPC::V_SETALLONESH: + case PPC::V_SETALLONES: return true; } return false; Index: llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td +++ llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td @@ -840,12 +840,12 @@ "xxlxor $XT, $XA, $XB", IIC_VecGeneral, [(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>; } // isCommutable - let isCodeGenOnly = 1 in - def XXLXORz : XX3Form_Zero<60, 154, (outs vsrc:$XT), (ins), + + let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, + isReMaterializable = 1 in { + def XXLXORz : XX3Form_Zero<60, 154, (outs vsrc:$XT), (ins), "xxlxor $XT, $XT, $XT", IIC_VecGeneral, [(set v4i32:$XT, (v4i32 immAllZerosV))]>; - - let isCodeGenOnly = 1 in { def XXLXORdpz : XX3Form_SetZero<60, 154, (outs vsfrc:$XT), (ins), "xxlxor $XT, $XT, $XT", IIC_VecGeneral, Index: llvm/trunk/test/CodeGen/PowerPC/optimize-andiso.ll =================================================================== --- llvm/trunk/test/CodeGen/PowerPC/optimize-andiso.ll +++ llvm/trunk/test/CodeGen/PowerPC/optimize-andiso.ll @@ -6,11 +6,9 @@ define float @floatundisf(i64 %a) { ; CHECK-LABEL: floatundisf: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_2 -; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: xxlxor f1, f1, f1 -; CHECK-NEXT: blr -; CHECK-NEXT: .LBB0_2: # %sw.epilog +; CHECK-NEXT: bclr 12, 4*cr5+lt, 0 +; CHECK-NEXT: # %bb.1: # %sw.epilog ; CHECK-NEXT: addi r3, r3, 1 ; CHECK-NEXT: li r5, 2 ; CHECK-NEXT: andis. r4, r3, 1024 Index: llvm/trunk/test/CodeGen/PowerPC/pr36292.ll =================================================================== --- llvm/trunk/test/CodeGen/PowerPC/pr36292.ll +++ llvm/trunk/test/CodeGen/PowerPC/pr36292.ll @@ -8,25 +8,22 @@ ; CHECK-LABEL: test: ; CHECK: # %bb.0: ; CHECK-NEXT: mflr 0 -; CHECK-NEXT: .cfi_def_cfa_offset 80 +; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_offset lr, 16 -; CHECK-NEXT: .cfi_offset r29, -32 -; CHECK-NEXT: .cfi_offset r30, -24 -; CHECK-NEXT: .cfi_offset f31, -8 -; CHECK-NEXT: std 29, -32(1) # 8-byte Folded Spill -; CHECK-NEXT: std 30, -24(1) # 8-byte Folded Spill -; CHECK-NEXT: stfd 31, -8(1) # 8-byte Folded Spill +; CHECK-NEXT: .cfi_offset r29, -24 +; CHECK-NEXT: .cfi_offset r30, -16 +; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill +; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-NEXT: std 0, 16(1) -; CHECK-NEXT: stdu 1, -80(1) +; CHECK-NEXT: stdu 1, -64(1) ; CHECK-NEXT: ld 29, 0(3) -; CHECK-NEXT: ld 30, 40(1) -; CHECK-NEXT: xxlxor 31, 31, 31 +; CHECK-NEXT: ld 30, 32(1) ; CHECK-NEXT: cmpld 30, 29 ; CHECK-NEXT: bge- 0, .LBB0_2 ; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB0_1: # %bounds.ok -; CHECK: fmr 1, 31 -; CHECK-NEXT: lfsx 2, 0, 3 +; CHECK: lfsx 2, 0, 3 +; CHECK-NEXT: xxlxor 1, 1, 1 ; CHECK-NEXT: bl fmodf ; CHECK-NEXT: nop ; CHECK-NEXT: addi 30, 30, 1 @@ -34,7 +31,7 @@ ; CHECK-NEXT: cmpld 30, 29 ; CHECK-NEXT: blt+ 0, .LBB0_1 ; CHECK-NEXT: .LBB0_2: # %bounds.fail -; CHECK-NEXT: std 30, 40(1) +; CHECK-NEXT: std 30, 32(1) %pos = alloca i64, align 8 br label %forcond Index: llvm/trunk/test/CodeGen/PowerPC/vsx-infl-copy1.ll =================================================================== --- llvm/trunk/test/CodeGen/PowerPC/vsx-infl-copy1.ll +++ llvm/trunk/test/CodeGen/PowerPC/vsx-infl-copy1.ll @@ -11,15 +11,11 @@ br label %vector.body ; CHECK-LABEL: @_Z8example9Pj -; CHECK: vmr -; CHECK: vmr -; CHECK: vmr -; CHECK: vmr -; CHECK: vmr -; CHECK: vmr -; CHECK: vmr -; CHECK: vmr -; CHECK: vmr +; CHECK: xxlxor +; CHECK: xxlxor +; CHECK: xxlxor +; CHECK: xxlxor +; CHECK: xxlxor vector.body: ; preds = %vector.body, %entry %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]