diff --git a/clang/test/CodeGenCXX/discard-name-values.cpp b/clang/test/CodeGenCXX/discard-name-values.cpp
--- a/clang/test/CodeGenCXX/discard-name-values.cpp
+++ b/clang/test/CodeGenCXX/discard-name-values.cpp
@@ -10,7 +10,7 @@
   // CHECK: br i1 %pred, label %if.then, label %if.end
 
   if (pred) {
-    // DISCARDVALUE: ; <label>:2:
+    // DISCARDVALUE: 2:
     // DISCARDVALUE-NEXT: tail call void @branch()
     // DISCARDVALUE-NEXT: br label %3
 
@@ -20,7 +20,7 @@
     branch();
   }
 
-  // DISCARDVALUE: ; <label>:3:
+  // DISCARDVALUE: 3:
   // DISCARDVALUE-NEXT: ret i1 %0
 
   // CHECK: if.end:
diff --git a/llgo/test/irgen/imports.go b/llgo/test/irgen/imports.go
--- a/llgo/test/irgen/imports.go
+++ b/llgo/test/irgen/imports.go
@@ -13,7 +13,7 @@
 // CHECK-NEXT: %[[N:.*]] = load i1, i1* @"init$guard"
 // CHECK-NEXT: br i1 %[[N]], label %{{.*}}, label %[[L:.*]]
 
-// CHECK: ; <label>:[[L]]
+// CHECK: [[L]]:
 // CHECK-NEXT: call void @__go_register_gc_roots
 // CHECK-NEXT: store i1 true, i1* @"init$guard"
 // CHECK-NEXT: call void @fmt..import(i8* undef)
diff --git a/llvm/lib/AsmParser/LLLexer.cpp b/llvm/lib/AsmParser/LLLexer.cpp
--- a/llvm/lib/AsmParser/LLLexer.cpp
+++ b/llvm/lib/AsmParser/LLLexer.cpp
@@ -1047,7 +1047,17 @@
   for (; isdigit(static_cast<unsigned char>(CurPtr[0])); ++CurPtr)
     /*empty*/;
 
-  // Check to see if this really is a label afterall, e.g. "-1:".
+  // Check if this is a fully-numeric label:
+  if (isdigit(TokStart[0]) && CurPtr[0] == ':') {
+    uint64_t Val = atoull(TokStart, CurPtr);
+    ++CurPtr; // Skip the colon.
+    if ((unsigned)Val != Val)
+      Error("invalid value number (too large)!");
+    UIntVal = unsigned(Val);
+    return lltok::LabelID;
+  }
+
+  // Check to see if this really is a string label, e.g. "-1:".
   if (isLabelChar(CurPtr[0]) || CurPtr[0] == ':') {
     if (const char *End = isLabelTail(CurPtr)) {
       StrVal.assign(TokStart, End-1);
diff --git a/llvm/lib/AsmParser/LLParser.h b/llvm/lib/AsmParser/LLParser.h
--- a/llvm/lib/AsmParser/LLParser.h
+++ b/llvm/lib/AsmParser/LLParser.h
@@ -445,7 +445,7 @@
       /// DefineBB - Define the specified basic block, which is either named or
       /// unnamed.  If there is an error, this returns null otherwise it returns
       /// the block being defined.
-      BasicBlock *DefineBB(const std::string &Name, LocTy Loc);
+      BasicBlock *DefineBB(const std::string &Name, int NameID, LocTy Loc);
 
       bool resolveForwardRefBlockAddresses();
     };
diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp
--- a/llvm/lib/AsmParser/LLParser.cpp
+++ b/llvm/lib/AsmParser/LLParser.cpp
@@ -2923,13 +2923,27 @@
 /// unnamed.  If there is an error, this returns null otherwise it returns
 /// the block being defined.
 BasicBlock *LLParser::PerFunctionState::DefineBB(const std::string &Name,
+                                                 int NameID,
                                                  LocTy Loc) {
   BasicBlock *BB;
-  if (Name.empty())
+  if (Name.empty()) {
+    if (NameID != -1 && unsigned(NameID) != NumberedVals.size()) {
+      P.Error(Loc, "label expected to be numbered '%" +
+                   Twine(NumberedVals.size()) + "'");
+      return nullptr;
+    }
     BB = GetBB(NumberedVals.size(), Loc);
-  else
+    if (!BB) {
+      P.Error(Loc, "unable to create block numbered " + Twine(NumberedVals.size()));
+      return nullptr;
+    }
+  } else {
     BB = GetBB(Name, Loc);
-  if (!BB) return nullptr; // Already diagnosed error.
+    if (!BB) {
+      P.Error(Loc, "unable to create block named '" + Name + "'");
+      return nullptr;
+    }
+  }
 
   // Move the block to the end of the function.  Forward ref'd blocks are
   // inserted wherever they happen to be referenced.
@@ -5477,20 +5491,23 @@
 }
 
 /// ParseBasicBlock
-///   ::= LabelStr? Instruction*
+///   ::= LabelStr|LabelID? Instruction*
 bool LLParser::ParseBasicBlock(PerFunctionState &PFS) {
   // If this basic block starts out with a name, remember it.
   std::string Name;
+  int NameID = -1;
   LocTy NameLoc = Lex.getLoc();
   if (Lex.getKind() == lltok::LabelStr) {
     Name = Lex.getStrVal();
     Lex.Lex();
+  } else if (Lex.getKind() == lltok::LabelID) {
+    NameID = Lex.getUIntVal();
+    Lex.Lex();
   }
 
-  BasicBlock *BB = PFS.DefineBB(Name, NameLoc);
+  BasicBlock *BB = PFS.DefineBB(Name, NameID, NameLoc);
   if (!BB)
-    return Error(NameLoc,
-                 "unable to create block named '" + Name + "'");
+    return true;
 
   std::string NameStr;
 
@@ -5560,7 +5577,7 @@
   Lex.Lex();  // Eat the keyword.
 
   switch (Token) {
-  default:                    return Error(Loc, "expected instruction opcode");
+    default:                    return Error(Loc, "expected instruction opcode");
   // Terminator Instructions.
   case lltok::kw_unreachable: Inst = new UnreachableInst(Context); return false;
   case lltok::kw_ret:         return ParseRet(Inst, BB, PFS);
diff --git a/llvm/lib/AsmParser/LLToken.h b/llvm/lib/AsmParser/LLToken.h
--- a/llvm/lib/AsmParser/LLToken.h
+++ b/llvm/lib/AsmParser/LLToken.h
@@ -421,6 +421,7 @@
   kw_varFlags,
 
   // Unsigned Valued tokens (UIntVal).
+  LabelID,    // 42:
   GlobalID,   // @42
   LocalVarID, // %42
   AttrGrpID,  // #42
diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp
--- a/llvm/lib/IR/AsmWriter.cpp
+++ b/llvm/lib/IR/AsmWriter.cpp
@@ -3477,23 +3477,24 @@
 
 /// printBasicBlock - This member is called for each basic block in a method.
 void AssemblyWriter::printBasicBlock(const BasicBlock *BB) {
+  bool IsEntryBlock = BB == &BB->getParent()->getEntryBlock();
   if (BB->hasName()) {              // Print out the label if it exists...
     Out << "\n";
     PrintLLVMName(Out, BB->getName(), LabelPrefix);
     Out << ':';
-  } else if (!BB->use_empty()) {      // Don't print block # of no uses...
-    Out << "\n; <label>:";
+  } else if (!IsEntryBlock) {
+    Out << "\n";
     int Slot = Machine.getLocalSlot(BB);
     if (Slot != -1)
       Out << Slot << ":";
     else
-      Out << "<badref>";
+      Out << "<badref>:";
   }
 
   if (!BB->getParent()) {
     Out.PadToColumn(50);
     Out << "; Error: Block without parent!";
-  } else if (BB != &BB->getParent()->getEntryBlock()) {  // Not the entry block?
+  } else if (!IsEntryBlock) {  // Not the entry block?
     // Output predecessors for the block.
     Out.PadToColumn(50);
     Out << ";";
diff --git a/llvm/test/Analysis/DominanceFrontier/new_pm_test.ll b/llvm/test/Analysis/DominanceFrontier/new_pm_test.ll
--- a/llvm/test/Analysis/DominanceFrontier/new_pm_test.ll
+++ b/llvm/test/Analysis/DominanceFrontier/new_pm_test.ll
@@ -3,48 +3,48 @@
 
 define void @a_linear_impl_fig_1() nounwind {
 0:
-  br label %"1"
+  br label %1
 1:
-  br label %"2"
+  br label %2
 2:
-  br label %"3"
+  br label %3
 3:
-  br i1 1, label %"13", label %"4"
+  br i1 1, label %12, label %4
 4:
-  br i1 1, label %"5", label %"1"
+  br i1 1, label %5, label %1
 5:
-  br i1 1, label %"8", label %"6"
+  br i1 1, label %8, label %6
 6:
-  br i1 1, label %"7", label %"4"
+  br i1 1, label %7, label %4
 7:
   ret void
 8:
-  br i1 1, label %"9", label %"1"
+  br i1 1, label %9, label %1
 9:
-  br label %"10"
+  br label %10
 10:
-  br i1 1, label %"12", label %"11"
+  br i1 1, label %13, label %11
 11:
-  br i1 1, label %"9", label %"8"
-13:
-  br i1 1, label %"2", label %"1"
+  br i1 1, label %9, label %8
 12:
-   switch i32 0, label %"1" [ i32 0, label %"9"
-                              i32 1, label %"8"]
+  br i1 1, label %2, label %1
+13:
+   switch i32 0, label %1 [ i32 0, label %9
+                              i32 1, label %8]
 }
 
 ; CHECK: DominanceFrontier for function: a_linear_impl_fig_1
-; CHECK-DAG:  DomFrontier for BB %"0" is:
-; CHECK-DAG:  DomFrontier for BB %"11" is:   %"{{[8|9]}}" %"{{[8|9]}}"
-; CHECK-DAG:  DomFrontier for BB %"1" is:    %"1"
-; CHECK-DAG:  DomFrontier for BB %"2" is:    %"{{[1|2]}}" %"{{[1|2]}}"
-; CHECK-DAG:  DomFrontier for BB %"3" is:    %"{{[1|2]}}" %"{{[1|2]}}"
-; CHECK-DAG:  DomFrontier for BB %"13" is:   %"{{[1|2]}}" %"{{[1|2]}}"
-; CHECK-DAG:  DomFrontier for BB %"4" is:    %"{{[1|4]}}" %"{{[1|4]}}"
-; CHECK-DAG:  DomFrontier for BB %"5" is:    %"{{[1|4]}}" %"{{[1|4]}}"
-; CHECK-DAG:  DomFrontier for BB %"8" is:    %"{{[1|8]}}" %"{{[1|8]}}"
-; CHECK-DAG:  DomFrontier for BB %"6" is:    %"4"
-; CHECK-DAG:  DomFrontier for BB %"7" is:
-; CHECK-DAG:  DomFrontier for BB %"9" is:    %"{{[1|8|9]}}" %"{{[1|8|9]}}" %"{{[1|8|9]}}"
-; CHECK-DAG:  DomFrontier for BB %"10" is:   %"{{[1|8|9]}}" %"{{[1|8|9]}}" %"{{[1|8|9]}}"
-; CHECK-DAG:  DomFrontier for BB %"12" is:   %"{{[1|8|9]}}" %"{{[1|8|9]}}" %"{{[1|8|9]}}"
+; CHECK-DAG:  DomFrontier for BB %0 is:
+; CHECK-DAG:  DomFrontier for BB %11 is:   %{{[8|9]}} %{{[8|9]}}
+; CHECK-DAG:  DomFrontier for BB %1 is:    %1
+; CHECK-DAG:  DomFrontier for BB %2 is:    %{{[1|2]}} %{{[1|2]}}
+; CHECK-DAG:  DomFrontier for BB %3 is:    %{{[1|2]}} %{{[1|2]}}
+; CHECK-DAG:  DomFrontier for BB %12 is:   %{{[1|2]}} %{{[1|2]}}
+; CHECK-DAG:  DomFrontier for BB %4 is:    %{{[1|4]}} %{{[1|4]}}
+; CHECK-DAG:  DomFrontier for BB %5 is:    %{{[1|4]}} %{{[1|4]}}
+; CHECK-DAG:  DomFrontier for BB %8 is:    %{{[1|8]}} %{{[1|8]}}
+; CHECK-DAG:  DomFrontier for BB %6 is:    %4
+; CHECK-DAG:  DomFrontier for BB %7 is:
+; CHECK-DAG:  DomFrontier for BB %9 is:    %{{[1|8|9]}} %{{[1|8|9]}} %{{[1|8|9]}}
+; CHECK-DAG:  DomFrontier for BB %10 is:   %{{[1|8|9]}} %{{[1|8|9]}} %{{[1|8|9]}}
+; CHECK-DAG:  DomFrontier for BB %13 is:   %{{[1|8|9]}} %{{[1|8|9]}} %{{[1|8|9]}}
diff --git a/llvm/test/Analysis/RegionInfo/cond_loop.ll b/llvm/test/Analysis/RegionInfo/cond_loop.ll
--- a/llvm/test/Analysis/RegionInfo/cond_loop.ll
+++ b/llvm/test/Analysis/RegionInfo/cond_loop.ll
@@ -7,18 +7,18 @@
 ; RUN: opt < %s -passes='print<regions>' 2>&1 | FileCheck %s
 
 define void @normal_condition() nounwind {
-5:
+"5":
         br label %"0"
 
-0:
+"0":
 	br label %"1"
-1:
+"1":
 	br i1 1, label %"2", label %"3"
-2:
+"2":
 	ret void
-3:
+"3":
 	br i1 1, label %"1", label %"4"
-4:
+"4":
         br label %"0"
 }
 
diff --git a/llvm/test/Analysis/RegionInfo/condition_forward_edge.ll b/llvm/test/Analysis/RegionInfo/condition_forward_edge.ll
--- a/llvm/test/Analysis/RegionInfo/condition_forward_edge.ll
+++ b/llvm/test/Analysis/RegionInfo/condition_forward_edge.ll
@@ -7,13 +7,13 @@
 ; RUN: opt < %s -passes='print<regions>' 2>&1 | FileCheck %s
 
 define void @normal_condition() nounwind {
-0:
+"0":
 	br label %"1"
-1:
+"1":
 	br i1 1, label %"2", label %"3"
-2:
+"2":
 	br label %"3"
-3:
+"3":
 	ret void
 }
 ; CHECK-NOT: =>
diff --git a/llvm/test/Analysis/RegionInfo/condition_same_exit.ll b/llvm/test/Analysis/RegionInfo/condition_same_exit.ll
--- a/llvm/test/Analysis/RegionInfo/condition_same_exit.ll
+++ b/llvm/test/Analysis/RegionInfo/condition_same_exit.ll
@@ -7,16 +7,16 @@
 ; RUN: opt < %s -passes='print<regions>' 2>&1 | FileCheck %s
 
 define void @normal_condition() nounwind {
-0:
+"0":
 	br i1 1, label %"1", label %"4"
 
-1:
+"1":
 	br i1 1, label %"2", label %"3"
-2:
+"2":
 	br label %"4"
-3:
+"3":
 	br label %"4"
-4:
+"4":
 	ret void
 }
 ; CHECK-NOT: =>
diff --git a/llvm/test/Analysis/RegionInfo/condition_simple.ll b/llvm/test/Analysis/RegionInfo/condition_simple.ll
--- a/llvm/test/Analysis/RegionInfo/condition_simple.ll
+++ b/llvm/test/Analysis/RegionInfo/condition_simple.ll
@@ -7,15 +7,15 @@
 ; RUN: opt < %s -passes='print<regions>' 2>&1 | FileCheck %s
 
 define void @normal_condition() nounwind {
-0:
+"0":
 	br label %"1"
-1:
+"1":
 	br i1 1, label %"2", label %"3"
-2:
+"2":
 	br label %"4"
-3:
+"3":
 	br label %"4"
-4:
+"4":
 	ret void
 }
 
diff --git a/llvm/test/Analysis/RegionInfo/infinite_loop.ll b/llvm/test/Analysis/RegionInfo/infinite_loop.ll
--- a/llvm/test/Analysis/RegionInfo/infinite_loop.ll
+++ b/llvm/test/Analysis/RegionInfo/infinite_loop.ll
@@ -4,16 +4,16 @@
 
 define void @normal_condition() nounwind {
 0:
-	br label %"1"
+	br label %1
 1:
-	br i1 1, label %"2", label %"3"
+	br i1 1, label %2, label %3
 2:
-	br label %"2"
+	br label %2
 3:
-	br label %"4"
+	br label %4
 4:
 	ret void
 }
 ; CHECK-NOT: =>
 ; CHECK: [0] 0 => <Function Return>
-; STAT: 1 region - The # of regions
\ No newline at end of file
+; STAT: 1 region - The # of regions
diff --git a/llvm/test/Analysis/RegionInfo/infinite_loop_2.ll b/llvm/test/Analysis/RegionInfo/infinite_loop_2.ll
--- a/llvm/test/Analysis/RegionInfo/infinite_loop_2.ll
+++ b/llvm/test/Analysis/RegionInfo/infinite_loop_2.ll
@@ -5,23 +5,23 @@
 ; RUN: opt -regions -print-region-style=rn  -analyze < %s 2>&1 | FileCheck -check-prefix=RNIT %s
 
 define void @normal_condition() nounwind {
-0:
+"0":
 	br label %"1"
-1:
+"1":
 	br i1 1, label %"2", label %"3"
-2:
+"2":
 	br label %"5"
-5:
+"5":
 	br i1 1, label %"11", label %"12"
-11:
+"11":
         br label %"6"
-12:
+"12":
         br label %"6"
-6:
+"6":
         br label %"2"
-3:
+"3":
 	br label %"4"
-4:
+"4":
 	ret void
 }
 ; CHECK-NOT: =>
diff --git a/llvm/test/Analysis/RegionInfo/infinite_loop_3.ll b/llvm/test/Analysis/RegionInfo/infinite_loop_3.ll
--- a/llvm/test/Analysis/RegionInfo/infinite_loop_3.ll
+++ b/llvm/test/Analysis/RegionInfo/infinite_loop_3.ll
@@ -6,35 +6,35 @@
 ; RUN: opt -regions -print-region-style=rn  -analyze < %s 2>&1 | FileCheck -check-prefix=RNIT %s
 
 define void @normal_condition() nounwind {
-0:
+"0":
 	br label %"7"
-7:
+"7":
 	br i1 1, label %"1", label %"8"
-1:
+"1":
 	br i1 1, label %"2", label %"3"
-2:
+"2":
 	br label %"5"
-5:
+"5":
 	br i1 1, label %"11", label %"12"
-11:
+"11":
         br label %"6"
-12:
+"12":
         br label %"6"
-6:
+"6":
         br label %"2"
-8:
+"8":
 	br label %"9"
-9:
+"9":
 	br i1 1, label %"13", label %"14"
-13:
+"13":
         br label %"10"
-14:
+"14":
         br label %"10"
-10:
+"10":
         br label %"8"
-3:
+"3":
 	br label %"4"
-4:
+"4":
 	ret void
 }
 ; CHECK-NOT: =>
diff --git a/llvm/test/Analysis/RegionInfo/infinite_loop_4.ll b/llvm/test/Analysis/RegionInfo/infinite_loop_4.ll
--- a/llvm/test/Analysis/RegionInfo/infinite_loop_4.ll
+++ b/llvm/test/Analysis/RegionInfo/infinite_loop_4.ll
@@ -5,35 +5,35 @@
 ; RUN: opt -regions -print-region-style=rn  -analyze < %s 2>&1 | FileCheck -check-prefix=RNIT %s
 
 define void @normal_condition() nounwind {
-0:
+"0":
 	br label %"7"
-7:
+"7":
 	br i1 1, label %"1", label %"8"
-1:
+"1":
 	br i1 1, label %"2", label %"3"
-2:
+"2":
 	br label %"5"
-5:
+"5":
 	br i1 1, label %"11", label %"12"
-11:
+"11":
         br label %"6"
-12:
+"12":
         br label %"6"
-6:
+"6":
 	br i1 1, label %"2", label %"10"
-8:
+"8":
 	br label %"9"
-9:
+"9":
 	br i1 1, label %"13", label %"14"
-13:
+"13":
         br label %"10"
-14:
+"14":
         br label %"10"
-10:
+"10":
         br label %"8"
-3:
+"3":
 	br label %"4"
-4:
+"4":
 	ret void
 }
 ; CHECK-NOT: =>
@@ -48,4 +48,4 @@
 ; BBIT: 5, 11, 12,
 ; RNIT: 0, 7, 1, 2 => 10, 10, 8, 9, 13, 14, 3, 4,
 ; RNIT: 2, 5 => 6, 6,
-; RNIT: 5, 11, 12,
\ No newline at end of file
+; RNIT: 5, 11, 12,
diff --git a/llvm/test/Analysis/RegionInfo/infinite_loop_5_a.ll b/llvm/test/Analysis/RegionInfo/infinite_loop_5_a.ll
--- a/llvm/test/Analysis/RegionInfo/infinite_loop_5_a.ll
+++ b/llvm/test/Analysis/RegionInfo/infinite_loop_5_a.ll
@@ -1,19 +1,19 @@
 ; RUN: opt -regions -analyze < %s | FileCheck %s
 
 define void @normal_condition() nounwind {
-0:
+"0":
     br label %"7"
-7:
+"7":
     br i1 1, label %"1", label %"8"
-1:
+"1":
     br i1 1, label %"6", label %"3"
-6:
+"6":
     br label %"8"
-8:
+"8":
     br label %"8"
-3:
+"3":
     br label %"4"
-4:
+"4":
     ret void
 }
 
diff --git a/llvm/test/Analysis/RegionInfo/infinite_loop_5_b.ll b/llvm/test/Analysis/RegionInfo/infinite_loop_5_b.ll
--- a/llvm/test/Analysis/RegionInfo/infinite_loop_5_b.ll
+++ b/llvm/test/Analysis/RegionInfo/infinite_loop_5_b.ll
@@ -1,21 +1,21 @@
 ; RUN: opt -regions -analyze < %s | FileCheck %s
 
 define void @normal_condition() nounwind {
-0:
+"0":
     br label %"7"
-7:
+"7":
     br i1 1, label %"1", label %"9"
-9:
+"9":
     br label %"8"
-1:
+"1":
     br i1 1, label %"6", label %"3"
-6:
+"6":
     br label %"9"
-8:
+"8":
     br label %"8"
-3:
+"3":
     br label %"4"
-4:
+"4":
     ret void
 }
 
diff --git a/llvm/test/Analysis/RegionInfo/infinite_loop_5_c.ll b/llvm/test/Analysis/RegionInfo/infinite_loop_5_c.ll
--- a/llvm/test/Analysis/RegionInfo/infinite_loop_5_c.ll
+++ b/llvm/test/Analysis/RegionInfo/infinite_loop_5_c.ll
@@ -1,19 +1,19 @@
 ; RUN: opt -regions -analyze < %s | FileCheck %s
 
 define void @normal_condition() nounwind {
-0:
+"0":
     br label %"7"
-7:
+"7":
     br i1 1, label %"1", label %"8"
-1:
+"1":
     br i1 1, label %"6", label %"3"
-6:
+"6":
     br label %"8"
-8:
+"8":
     br i1 1, label %"8", label %"7"
-3:
+"3":
     br label %"4"
-4:
+"4":
     ret void
 }
 
diff --git a/llvm/test/Analysis/RegionInfo/loop_with_condition.ll b/llvm/test/Analysis/RegionInfo/loop_with_condition.ll
--- a/llvm/test/Analysis/RegionInfo/loop_with_condition.ll
+++ b/llvm/test/Analysis/RegionInfo/loop_with_condition.ll
@@ -8,25 +8,25 @@
 ; RUN: opt < %s -passes='print<regions>' 2>&1 | FileCheck %s
 
 define void @normal_condition() nounwind {
-0:
+"0":
         br label %"1"
-1:
+"1":
 	br i1 1, label %"6", label %"2"
-2:
+"2":
 	br i1 1, label %"3", label %"4"
-3:
+"3":
 	br label %"5"
-4:
+"4":
 	br label %"5"
-5:
+"5":
         br label %"8"
-8:
+"8":
         br i1 1, label %"7", label %"9"
-9:
+"9":
         br label %"2"
-7:
+"7":
         br label %"6"
-6:
+"6":
 	ret void
 }
 
diff --git a/llvm/test/Analysis/RegionInfo/mix_1.ll b/llvm/test/Analysis/RegionInfo/mix_1.ll
--- a/llvm/test/Analysis/RegionInfo/mix_1.ll
+++ b/llvm/test/Analysis/RegionInfo/mix_1.ll
@@ -8,45 +8,45 @@
 ; RUN: opt < %s -passes='print<regions>' 2>&1 | FileCheck %s
 
 define void @a_linear_impl_fig_1() nounwind {
-0:
+"0":
 
 	br i1 1, label %"1", label %"15"
-1:
+"1":
  	switch i32 0, label %"2" [ i32 0, label %"3"
                                   i32 1, label %"7"]
-2:
+"2":
 	br label %"4"
-3:
+"3":
 	br label %"5"
-4:
+"4":
 	br label %"6"
-5:
+"5":
 	br label %"6"
-6:
+"6":
 	br label %"7"
-7:
+"7":
 	br label %"15"
-15:
+"15":
 	br label %"8"
-8:
+"8":
 	br label %"16"
-16:
+"16":
         br label %"9"
-9:
+"9":
 	br i1 1, label %"10", label %"11"
-11:
+"11":
 	br i1 1, label %"13", label %"12"
-13:
+"13":
 	br label %"14"
-12:
+"12":
 	br label %"14"
-14:
+"14":
 	br label %"8"
-10:
+"10":
         br label %"17"
-17:
+"17":
         br label %"18"
-18:
+"18":
         ret void
 }
 
diff --git a/llvm/test/Analysis/RegionInfo/paper.ll b/llvm/test/Analysis/RegionInfo/paper.ll
--- a/llvm/test/Analysis/RegionInfo/paper.ll
+++ b/llvm/test/Analysis/RegionInfo/paper.ll
@@ -7,33 +7,33 @@
 ; RUN: opt < %s -passes='print<regions>' 2>&1 | FileCheck %s
 
 define void @a_linear_impl_fig_1() nounwind {
-0:
+"0":
         br label %"1"
-1:
+"1":
 	br label %"2"
-2:
+"2":
 	br label %"3"
-3:
+"3":
 	br i1 1, label %"13", label %"4"
-4:
+"4":
 	br i1 1, label %"5", label %"1"
-5:
+"5":
 	br i1 1, label %"8", label %"6"
-6:
+"6":
 	br i1 1, label %"7", label %"4"
-7:
+"7":
 	ret void
-8:
+"8":
 	br i1 1, label %"9", label %"1"
-9:
+"9":
 	br label %"10"
-10:
+"10":
 	br i1 1, label %"12", label %"11"
-11:
+"11":
 	br i1 1, label %"9", label %"8"
-13:
+"13":
 	br i1 1, label %"2", label %"1"
-12:
+"12":
  	switch i32 0, label %"1" [ i32 0, label %"9"
                                   i32 1, label %"8"]
 }
diff --git a/llvm/test/Assembler/block-labels.ll b/llvm/test/Assembler/block-labels.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/Assembler/block-labels.ll
@@ -0,0 +1,48 @@
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s --match-full-lines
+; RUN: verify-uselistorder %s
+
+define i32 @test1(i32 %X) {
+; Implicit entry label. Not printed on output.
+  %1 = alloca i32
+  br label %2
+; Implicit label ids still allowed.
+  br label %3
+3: ; Explicit numeric label
+  br label %"2"
+"2": ; string label, quoted number
+  br label %-3
+-3: ; numeric-looking, but actually string, label
+  br label %-N-
+-N-:
+  br label %$N
+$N:
+  %4 = add i32 1, 1
+  ret i32 %4
+}
+
+; CHECK-LABEL: define i32 @test1(i32 %X) {
+; CHECK-NEXT:   %1 = alloca i32
+; CHECK-NEXT:   br label %2
+; CHECK:      2:       ; preds = %0
+; CHECK-NEXT:   br label %3
+; CHECK:      3:       ; preds = %2
+; CHECK-NEXT:   br label %"2"
+; CHECK:      "2":     ; preds = %3
+; CHECK-NEXT:   br label %-3
+; CHECK:      -3:      ; preds = %"2"
+; CHECK-NEXT:   br label %-N-
+; CHECK:      -N-:     ; preds = %-3
+; CHECK-NEXT:   br label %"$N"
+; CHECK:      "$N":    ; preds = %-N-
+; CHECK-NEXT:   %4 = add i32 1, 1
+; CHECK-NEXT:   ret i32 %4
+; CHECK-NEXT: }
+
+define void @test2(i32, i32) {
+; entry label id still not printed on output
+2:
+  ret void
+}
+
+; CHECK-LABEL: define void @test2(i32, i32) {
+; CHECK-NEXT:    ret void
diff --git a/llvm/test/Assembler/invalid-block-label-num.ll b/llvm/test/Assembler/invalid-block-label-num.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/Assembler/invalid-block-label-num.ll
@@ -0,0 +1,7 @@
+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+define void @f () {
+1:
+; CHECK: error: label expected to be numbered '%0'
+  ret void
+}
diff --git a/llvm/test/CodeGen/X86/atomic-pointer.ll b/llvm/test/CodeGen/X86/atomic-pointer.ll
--- a/llvm/test/CodeGen/X86/atomic-pointer.ll
+++ b/llvm/test/CodeGen/X86/atomic-pointer.ll
@@ -5,7 +5,7 @@
 ; CHECK: movl
 ; CHECK: movl
 ; CHECK: ret
-0:
+entry:
   %0 = load atomic i32*, i32** %a0 seq_cst, align 4
   ret i32* %0
 }
@@ -16,7 +16,7 @@
 ; CHECK: movl
 ; CHECK: xchgl
 ; CHECK: ret
-0:
-  store atomic i32* %a0, i32** %a1 seq_cst, align 4
+entry:
+store atomic i32* %a0, i32** %a1 seq_cst, align 4
   ret void
 }
diff --git a/llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll b/llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll
--- a/llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll
@@ -75,39 +75,39 @@
   %p = load <4 x float>*, <4 x float>** @v4f32, align 8
 ; STORE: [[MASK0:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 0
 ; STORE: br i1 [[MASK0]], label %[[THEN0:[0-9A-Za-z]+]], label %[[AFTER0:[0-9A-Za-z]+]]
-; STORE: <label>:[[THEN0]]:
+; STORE: [[THEN0]]:
 ; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
 ; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
 ; STORE: call void @__asan_store4(i64 [[PGEP0]])
 ; STORE: br label %[[AFTER0]]
-; STORE: <label>:[[AFTER0]]
+; STORE: [[AFTER0]]:
 
 ; STORE: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1
 ; STORE: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]]
-; STORE: <label>:[[THEN1]]:
+; STORE: [[THEN1]]:
 ; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1
 ; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64
 ; STORE: call void @__asan_store4(i64 [[PGEP1]])
 ; STORE: br label %[[AFTER1]]
-; STORE: <label>:[[AFTER1]]
+; STORE: [[AFTER1]]:
 
 ; STORE: [[MASK2:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 2
 ; STORE: br i1 [[MASK2]], label %[[THEN2:[0-9A-Za-z]+]], label %[[AFTER2:[0-9A-Za-z]+]]
-; STORE: <label>:[[THEN2]]:
+; STORE: [[THEN2]]:
 ; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2
 ; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64
 ; STORE: call void @__asan_store4(i64 [[PGEP2]])
 ; STORE: br label %[[AFTER2]]
-; STORE: <label>:[[AFTER2]]
+; STORE: [[AFTER2]]:
 
 ; STORE: [[MASK3:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 3
 ; STORE: br i1 [[MASK3]], label %[[THEN3:[0-9A-Za-z]+]], label %[[AFTER3:[0-9A-Za-z]+]]
-; STORE: <label>:[[THEN3]]:
+; STORE: [[THEN3]]:
 ; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3
 ; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64
 ; STORE: call void @__asan_store4(i64 [[PGEP3]])
 ; STORE: br label %[[AFTER3]]
-; STORE: <label>:[[AFTER3]]
+; STORE: [[AFTER3]]:
 
 ; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> %mask)
   tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> %mask)
@@ -203,39 +203,39 @@
   %p = load <4 x float>*, <4 x float>** @v4f32, align 8
 ; LOAD: [[MASK0:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 0
 ; LOAD: br i1 [[MASK0]], label %[[THEN0:[0-9A-Za-z]+]], label %[[AFTER0:[0-9A-Za-z]+]]
-; LOAD: <label>:[[THEN0]]:
+; LOAD: [[THEN0]]:
 ; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
 ; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
 ; LOAD: call void @__asan_load4(i64 [[PGEP0]])
 ; LOAD: br label %[[AFTER0]]
-; LOAD: <label>:[[AFTER0]]
+; LOAD: [[AFTER0]]:
 
 ; LOAD: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1
 ; LOAD: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]]
-; LOAD: <label>:[[THEN1]]:
+; LOAD: [[THEN1]]:
 ; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1
 ; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64
 ; LOAD: call void @__asan_load4(i64 [[PGEP1]])
 ; LOAD: br label %[[AFTER1]]
-; LOAD: <label>:[[AFTER1]]
+; LOAD: [[AFTER1]]:
 
 ; LOAD: [[MASK2:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 2
 ; LOAD: br i1 [[MASK2]], label %[[THEN2:[0-9A-Za-z]+]], label %[[AFTER2:[0-9A-Za-z]+]]
-; LOAD: <label>:[[THEN2]]:
+; LOAD: [[THEN2]]:
 ; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2
 ; LOAD: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64
 ; LOAD: call void @__asan_load4(i64 [[PGEP2]])
 ; LOAD: br label %[[AFTER2]]
-; LOAD: <label>:[[AFTER2]]
+; LOAD: [[AFTER2]]:
 
 ; LOAD: [[MASK3:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 3
 ; LOAD: br i1 [[MASK3]], label %[[THEN3:[0-9A-Za-z]+]], label %[[AFTER3:[0-9A-Za-z]+]]
-; LOAD: <label>:[[THEN3]]:
+; LOAD: [[THEN3]]:
 ; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3
 ; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64
 ; LOAD: call void @__asan_load4(i64 [[PGEP3]])
 ; LOAD: br label %[[AFTER3]]
-; LOAD: <label>:[[AFTER3]]
+; LOAD: [[AFTER3]]:
 
 ; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> %mask, <4 x float> %arg)
   %res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> %mask, <4 x float> %arg)
diff --git a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime-be.ll b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime-be.ll
--- a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime-be.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime-be.ll
@@ -159,14 +159,14 @@
 
   ; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 40, i8* %zz)
 
-  ; CHECK-LABEL: <label>
+  ; CHECK: {{^[0-9]+}}:
 
   ; CHECK-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0
   ; CHECK-NEXT: call void @__asan_set_shadow_f5(i64 [[OFFSET]], i64 128)
 
   ; CHECK-NOT: add i64 [[SHADOW_BASE]]
 
-  ; CHECK-LABEL: <label>
+  ; CHECK: {{^[0-9]+}}:
 
   ; 00000000
   ; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0
@@ -205,7 +205,7 @@
   ; CHECK-NOT: add i64 [[SHADOW_BASE]]
 
   ret void
-  ; CHECK-LABEL: <label>
+  ; CHECK: {{^[0-9]+}}:
   ; CHECK: ret void
 }
 
diff --git a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime.ll b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime.ll
--- a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime.ll
@@ -159,14 +159,14 @@
 
   ; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 40, i8* %zz)
 
-  ; CHECK-LABEL: <label>
+  ; CHECK: {{^[0-9]+}}:
 
   ; CHECK-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0
   ; CHECK-NEXT: call void @__asan_set_shadow_f5(i64 [[OFFSET]], i64 128)
 
   ; CHECK-NOT: add i64 [[SHADOW_BASE]]
 
-  ; CHECK-LABEL: <label>
+  ; CHECK: {{^[0-9]+}}:
 
   ; 00000000
   ; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0
@@ -205,7 +205,7 @@
   ; CHECK-NOT: add i64 [[SHADOW_BASE]]
 
   ret void
-  ; CHECK-LABEL: <label>
+  ; CHECK: {{^[0-9]+}}:
   ; CHECK: ret void
 }
 
diff --git a/llvm/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll b/llvm/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll
--- a/llvm/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll
@@ -12,14 +12,14 @@
 ; CHECK: entry:
 ; CHECK: load i32, i32* @__asan_option_detect_stack_use_after_return
 
-; CHECK: <label>:[[UAR_ENABLED_BB:[0-9]+]]
+; CHECK: [[UAR_ENABLED_BB:^[0-9]+]]:
 ; CHECK: [[FAKE_STACK_RT:%[0-9]+]] = call i64 @__asan_stack_malloc_
 
-; CHECK: <label>:[[FAKE_STACK_BB:[0-9]+]]
+; CHECK: [[FAKE_STACK_BB:^[0-9]+]]:
 ; CHECK: [[FAKE_STACK:%[0-9]+]] = phi i64 [ 0, %entry ], [ [[FAKE_STACK_RT]], %[[UAR_ENABLED_BB]] ]
 ; CHECK: icmp eq i64 [[FAKE_STACK]], 0
 
-; CHECK: <label>:[[NO_FAKE_STACK_BB:[0-9]+]]
+; CHECK: [[NO_FAKE_STACK_BB:^[0-9]+]]:
 ; CHECK: %MyAlloca = alloca i8, i64
 ; CHECK: [[ALLOCA:%[0-9]+]] = ptrtoint i8* %MyAlloca
 
diff --git a/llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll b/llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll
--- a/llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll
@@ -44,9 +44,9 @@
 ; CHECK-NOT: xor
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: call void @__msan_warning_noreturn
-; CHECK: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: xor
 ; CHECK: store
 ; CHECK: store i32 %x
diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
--- a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
@@ -39,10 +39,10 @@
 ; CHECK: store
 ; CHECK-ORIGINS: icmp
 ; CHECK-ORIGINS: br i1
-; CHECK-ORIGINS: <label>
+; CHECK-ORIGINS: {{^[0-9]+}}:
 ; CHECK-ORIGINS: store
 ; CHECK-ORIGINS: br label
-; CHECK-ORIGINS: <label>
+; CHECK-ORIGINS: {{^[0-9]+}}:
 ; CHECK: store
 ; CHECK: ret void
 
@@ -63,10 +63,10 @@
 ; CHECK: store {{.*}} align 32
 ; CHECK-ORIGINS: icmp
 ; CHECK-ORIGINS: br i1
-; CHECK-ORIGINS: <label>
+; CHECK-ORIGINS: {{^[0-9]+}}:
 ; CHECK-ORIGINS: store {{.*}} align 32
 ; CHECK-ORIGINS: br label
-; CHECK-ORIGINS: <label>
+; CHECK-ORIGINS: {{^[0-9]+}}:
 ; CHECK: store {{.*}} align 32
 ; CHECK: ret void
 
diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_kernel_basic.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_kernel_basic.ll
--- a/llvm/test/Instrumentation/MemorySanitizer/msan_kernel_basic.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/msan_kernel_basic.ll
@@ -40,10 +40,10 @@
 }
 
 ; CHECK-LABEL: @Store1
-; CHECK-LABEL: entry:
+; CHECK: entry:
 ; CHECK: @__msan_get_context_state()
 ; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
-; CHECK-LABEL: entry.split:
+; CHECK: entry.split:
 ; CHECK: [[BASE2:%[0-9]+]] = ptrtoint {{.*}} [[PARAM_SHADOW]]
 ; CHECK: [[BASE:%[0-9]+]] = ptrtoint {{.*}} [[PARAM_SHADOW]]
 ; CHECK: [[SHADOW:%[a-z0-9_]+]] = inttoptr {{.*}} [[BASE]]
@@ -51,18 +51,18 @@
 ; CHECK: load i64, i64* [[SHADOW]]
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK-LABEL: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: @__msan_metadata_ptr_for_store_1(i8* %p)
 ; CHECK: store i8
 ; If the new shadow is non-zero, jump to __msan_chain_origin()
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: @__msan_chain_origin
 ; Storing origin here:
 ; CHECK: store i32
 ; CHECK: br label
-; CHECK: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: store i8
 ; CHECK: ret void
 
@@ -73,28 +73,28 @@
 }
 
 ; CHECK-LABEL: @Store2
-; CHECK-LABEL: entry:
+; CHECK: entry:
 ; CHECK: @__msan_get_context_state()
 ; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
-; CHECK-LABEL: entry.split:
+; CHECK: entry.split:
 ; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
 ; Load the shadow of %p and check it
 ; CHECK: load i64
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK-LABEL: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: [[REG:%[0-9]+]] = bitcast i16* %p to i8*
 ; CHECK: @__msan_metadata_ptr_for_store_2(i8* [[REG]])
 ; CHECK: store i16
 ; If the new shadow is non-zero, jump to __msan_chain_origin()
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: @__msan_chain_origin
 ; Storing origin here:
 ; CHECK: store i32
 ; CHECK: br label
-; CHECK: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: store i16
 ; CHECK: ret void
 
@@ -106,28 +106,28 @@
 }
 
 ; CHECK-LABEL: @Store4
-; CHECK-LABEL: entry:
+; CHECK: entry:
 ; CHECK: @__msan_get_context_state()
 ; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
-; CHECK-LABEL: entry.split:
+; CHECK: entry.split:
 ; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
 ; Load the shadow of %p and check it
 ; CHECK: load i32
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK-LABEL: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: [[REG:%[0-9]+]] = bitcast i32* %p to i8*
 ; CHECK: @__msan_metadata_ptr_for_store_4(i8* [[REG]])
 ; CHECK: store i32
 ; If the new shadow is non-zero, jump to __msan_chain_origin()
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: @__msan_chain_origin
 ; Storing origin here:
 ; CHECK: store i32
 ; CHECK: br label
-; CHECK: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: store i32
 ; CHECK: ret void
 
@@ -138,28 +138,28 @@
 }
 
 ; CHECK-LABEL: @Store8
-; CHECK-LABEL: entry:
+; CHECK: entry:
 ; CHECK: @__msan_get_context_state()
 ; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
-; CHECK-LABEL: entry.split:
+; CHECK: entry.split:
 ; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
 ; Load the shadow of %p and check it
 ; CHECK: load i64
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK-LABEL: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: [[REG:%[0-9]+]] = bitcast i64* %p to i8*
 ; CHECK: @__msan_metadata_ptr_for_store_8(i8* [[REG]])
 ; CHECK: store i64
 ; If the new shadow is non-zero, jump to __msan_chain_origin()
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: @__msan_chain_origin
 ; Storing origin here:
 ; CHECK: store i32
 ; CHECK: br label
-; CHECK: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: store i64
 ; CHECK: ret void
 
@@ -170,28 +170,28 @@
 }
 
 ; CHECK-LABEL: @Store16
-; CHECK-LABEL: entry:
+; CHECK: entry:
 ; CHECK: @__msan_get_context_state()
 ; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
-; CHECK-LABEL: entry.split:
+; CHECK: entry.split:
 ; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
 ; Load the shadow of %p and check it
 ; CHECK: load i64
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK-LABEL: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: [[REG:%[0-9]+]] = bitcast i128* %p to i8*
 ; CHECK: @__msan_metadata_ptr_for_store_n(i8* [[REG]], i64 16)
 ; CHECK: store i128
 ; If the new shadow is non-zero, jump to __msan_chain_origin()
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: @__msan_chain_origin
 ; Storing origin here:
 ; CHECK: store i32
 ; CHECK: br label
-; CHECK: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: store i128
 ; CHECK: ret void
 
@@ -205,16 +205,16 @@
 }
 
 ; CHECK-LABEL: @Load1
-; CHECK-LABEL: entry:
+; CHECK: entry:
 ; CHECK: @__msan_get_context_state()
 ; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
-; CHECK-LABEL: entry.split:
+; CHECK: entry.split:
 ; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
 ; Load the shadow of %p and check it
 ; CHECK: load i64
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK-LABEL: <label>
+; CHECK: {{^[0-9]+}}:
 ; Load the value from %p. This is done before accessing the shadow
 ; to ease atomic handling.
 ; CHECK: load i8
@@ -231,16 +231,16 @@
 }
 
 ; CHECK-LABEL: @Load2
-; CHECK-LABEL: entry:
+; CHECK: entry:
 ; CHECK: @__msan_get_context_state()
 ; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
-; CHECK-LABEL: entry.split:
+; CHECK: entry.split:
 ; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
 ; Load the shadow of %p and check it
 ; CHECK: load i64
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK-LABEL: <label>
+; CHECK: {{^[0-9]+}}:
 ; Load the value from %p. This is done before accessing the shadow
 ; to ease atomic handling.
 ; CHECK: load i16
@@ -258,16 +258,16 @@
 }
 
 ; CHECK-LABEL: @Load4
-; CHECK-LABEL: entry:
+; CHECK: entry:
 ; CHECK: @__msan_get_context_state()
 ; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
-; CHECK-LABEL: entry.split:
+; CHECK: entry.split:
 ; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
 ; Load the shadow of %p and check it
 ; CHECK: load i64
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK-LABEL: <label>
+; CHECK: {{^[0-9]+}}:
 ; Load the value from %p. This is done before accessing the shadow
 ; to ease atomic handling.
 ; CHECK: load i32
@@ -284,16 +284,16 @@
 }
 
 ; CHECK-LABEL: @Load8
-; CHECK-LABEL: entry:
+; CHECK: entry:
 ; CHECK: @__msan_get_context_state()
 ; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
-; CHECK-LABEL: entry.split:
+; CHECK: entry.split:
 ; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
 ; Load the shadow of %p and check it
 ; CHECK: load i64
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK-LABEL: <label>
+; CHECK: {{^[0-9]+}}:
 ; Load the value from %p. This is done before accessing the shadow
 ; to ease atomic handling.
 ; CHECK: load i64
@@ -310,16 +310,16 @@
 }
 
 ; CHECK-LABEL: @Load16
-; CHECK-LABEL: entry:
+; CHECK: entry:
 ; CHECK: @__msan_get_context_state()
 ; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
-; CHECK-LABEL: entry.split:
+; CHECK: entry.split:
 ; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
 ; Load the shadow of %p and check it
 ; CHECK: load i64
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK-LABEL: <label>
+; CHECK: {{^[0-9]+}}:
 ; Load the value from %p. This is done before accessing the shadow
 ; to ease atomic handling.
 ; CHECK: load i128
@@ -359,7 +359,7 @@
 ; CHECK: [[VA_ARG_ORIGIN:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 3
 ; CHECK: [[VA_ARG_OVERFLOW_SIZE:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 4
 
-; CHECK-LABEL: entry.split:
+; CHECK: entry.split:
 ; CHECK: [[OSIZE:%[0-9]+]] = load i64, i64* [[VA_ARG_OVERFLOW_SIZE]]
 ; Register save area is 48 bytes for non-SSE builds.
 ; CHECK: [[SIZE:%[0-9]+]] = add i64 48, [[OSIZE]]
@@ -380,13 +380,13 @@
 
 ; CHECK-LABEL: @VarArgCaller
 
-; CHECK-LABEL: entry:
+; CHECK: entry:
 ; CHECK: @__msan_get_context_state()
 ; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
 ; CHECK: [[VA_ARG_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 2
 ; CHECK: [[VA_ARG_OVERFLOW_SIZE:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 4
 
-; CHECK-LABEL: entry.split:
+; CHECK: entry.split:
 ; CHECK: [[PARAM_SI:%[_a-z0-9]+]] = ptrtoint {{.*}} [[PARAM_SHADOW]]
 ; CHECK: [[ARG1_S:%[_a-z0-9]+]] = inttoptr i64 [[PARAM_SI]] to i64*
 ; First argument is initialized
diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_x86_bts_asm.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_x86_bts_asm.ll
--- a/llvm/test/Instrumentation/MemorySanitizer/msan_x86_bts_asm.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/msan_x86_bts_asm.ll
@@ -96,6 +96,6 @@
 ; CHECK: br i1 [[MSCMP]], label %[[IFTRUE:.*]], label {{.*}}
 
 ; If yes, raise a warning.
-; CHECK: <label>:[[IFTRUE]]
+; CHECK: [[IFTRUE]]:
 ; CHECK: call void @__msan_warning
 
diff --git a/llvm/test/Instrumentation/MemorySanitizer/store-origin.ll b/llvm/test/Instrumentation/MemorySanitizer/store-origin.ll
--- a/llvm/test/Instrumentation/MemorySanitizer/store-origin.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/store-origin.ll
@@ -74,7 +74,7 @@
 ; CHECK: store {{.*}}!dbg ![[DBG:[0-9]+]]
 ; CHECK: icmp
 ; CHECK: br i1
-; CHECK: <label>
+; CHECK: {{^[0-9]+}}:
 
 ; Origin tracking level 1: simply store the origin value
 ; CHECK-ORIGINS1: store i32 {{.*}}[[ORIGIN]],{{.*}}!dbg !{{.*}}[[DBG]]
@@ -84,6 +84,6 @@
 ; CHECK-ORIGINS2: store i32 {{.*}}[[ORIGIN2]],{{.*}}!dbg !{{.*}}[[DBG]]
 
 ; CHECK: br label{{.*}}!dbg !{{.*}}[[DBG]]
-; CHECK: <label>
+; CHECK: {{^[0-9]+}}:
 ; CHECK: store{{.*}}!dbg !{{.*}}[[DBG]]
 ; CHECK: ret void
diff --git a/llvm/test/Instrumentation/SanitizerCoverage/stack-depth.ll b/llvm/test/Instrumentation/SanitizerCoverage/stack-depth.ll
--- a/llvm/test/Instrumentation/SanitizerCoverage/stack-depth.ll
+++ b/llvm/test/Instrumentation/SanitizerCoverage/stack-depth.ll
@@ -29,7 +29,7 @@
 ; CHECK: [[lowest:%[^ \t]+]] = load [[intType]], [[intType]]* @__sancov_lowest_stack
 ; CHECK: [[cmp:%[^ \t]+]] = icmp ult [[intType]] [[frameInt]], [[lowest]]
 ; CHECK: br i1 [[cmp]], label %[[ifLabel:[^ \t]+]], label
-; CHECK: <label>:[[ifLabel]]:
+; CHECK: [[ifLabel]]:
 ; CHECK: store [[intType]] [[frameInt]], [[intType]]* @__sancov_lowest_stack
 ; CHECK: %call = call i32 @foo()
 ; CHECK: ret i32 %call
diff --git a/llvm/test/Transforms/GVNHoist/pr36787.ll b/llvm/test/Transforms/GVNHoist/pr36787.ll
--- a/llvm/test/Transforms/GVNHoist/pr36787.ll
+++ b/llvm/test/Transforms/GVNHoist/pr36787.ll
@@ -16,58 +16,58 @@
   invoke void @f0()
           to label %3 unwind label %1
 
-; <label>:1:
+1:
   %2 = landingpad { i8*, i32 }
           catch i8* bitcast (i8** @g to i8*)
           catch i8* null
   br label %16
 
-; <label>:3:
+3:
   br i1 undef, label %4, label %10
 
-;CHECK:       <label>:4
+;CHECK:       4:
 ;CHECK-NEXT:    %5 = load i32*, i32** undef, align 8
 ;CHECK-NEXT:    invoke void @f1()
 
-; <label>:4:
+4:
   %5 = load i32*, i32** undef, align 8
   invoke void @f1()
           to label %6 unwind label %1
 
-;CHECK:       <label>:6
+;CHECK:       6:
 ;CHECK-NEXT:    %7 = load i32*, i32** undef, align 8
 ;CHECK-NEXT:    %8 = load i32*, i32** undef, align 8
 
-; <label>:6:
+6:
   %7 = load i32*, i32** undef, align 8
   %8 = load i32*, i32** undef, align 8
   br i1 true, label %9, label %17
 
-; <label>:9:
+9:
   invoke void @f0()
           to label %10 unwind label %1
 
-; <label>:10:
+10:
   invoke void @f2()
           to label %11 unwind label %1
 
-; <label>:11:
+11:
   %12 = invoke signext i32 undef(i32* null, i32 signext undef, i1 zeroext undef)
           to label %13 unwind label %14
 
-; <label>:13:
+13:
   unreachable
 
-; <label>:14:
+14:
   %15 = landingpad { i8*, i32 }
           catch i8* bitcast (i8** @g to i8*)
           catch i8* null
   br label %16
 
-; <label>:16:
+16:
   unreachable
 
-; <label>:17:
+17:
   ret void
 
 ; uselistorder directives
diff --git a/llvm/test/Transforms/LowerSwitch/2014-06-23-PHIlowering.ll b/llvm/test/Transforms/LowerSwitch/2014-06-23-PHIlowering.ll
--- a/llvm/test/Transforms/LowerSwitch/2014-06-23-PHIlowering.ll
+++ b/llvm/test/Transforms/LowerSwitch/2014-06-23-PHIlowering.ll
@@ -2,10 +2,10 @@
 
 define i32 @test(i32 %arg) #0 {
 ; CHECK-LABEL: @test
-; CHECK: ; <label>:2
+; CHECK: 2:
 ; CHECK-NEXT:  %res.0 = phi i32 [ 1, %NodeBlock ], [ 2, %1 ]
 ; CHECK-NEXT:  br label %3
-; CHECK: ; <label>:5
+; CHECK: 5:
 ; CHECK-NEXT:   %res.3 = phi i32 [ 0, %NewDefault ], [ %res.2, %4 ]
 ; CHECK-NEXT:   %6 = add nsw i32 %res.3, 1
 ; CHECK-NEXT:   ret i32 %6
@@ -17,23 +17,23 @@
     i32 4, label %4
   ]
 
-; <label>:1
+1:
   br label %2
 
-; <label>:2
+2:
   %res.0 = phi i32 [ 1, %0 ], [ 2, %1 ]
   br label %3
 
-; <label>:3
+3:
   %res.1 = phi i32 [ 0, %0 ], [ %res.0, %2 ]
   %phitmp = add nsw i32 %res.1, 2
   br label %4
 
-; <label>:4
+4:
   %res.2 = phi i32 [ 1, %0 ], [ %phitmp, %3 ]
   br label %5
 
-; <label>:5
+5:
   %res.3 = phi i32 [ 0, %0 ], [ %res.2, %4 ]
   %6 = add nsw i32 %res.3, 1
   ret i32 %6