Index: lib/Target/Mips/MipsDelaySlotFiller.cpp
===================================================================
--- lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -725,6 +725,7 @@
     // but we don't have enough information to make that decision.
      if (InMicroMipsMode && TII->getInstSizeInBytes(*CurrI) == 2 &&
         (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch ||
+         Opcode == Mips::PseudoIndirectBranch_MM ||
          Opcode == Mips::PseudoReturn || Opcode == Mips::TAILCALL))
       continue;
      // Instructions LWP/SWP and MOVEP should not be in a delay slot as that
Index: test/CodeGen/Mips/pseudo-jump-fill.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/pseudo-jump-fill.ll
@@ -0,0 +1,35 @@
+; RUN: llc -mtriple=mipsel-linux-gnu -mattr=+micromips -relocation-model=pic < %s | FileCheck %s --check-prefixes=MIPS
+
+define i32 @test(i32 signext %x, i32 signext %c) {
+
+; MIPS:         jr
+; MIPS-NEXT:    nop
+
+entry:
+  switch i32 %c, label %sw.epilog [
+    i32 4, label %sw.bb5
+    i32 1, label %for.cond.cleanup
+    i32 2, label %sw.bb2
+    i32 3, label %sw.bb3
+  ]
+
+sw.bb2:                                           ; preds = %entry
+  %add = add nsw i32 %x, 1
+  br label %sw.epilog
+
+sw.bb3:                                           ; preds = %entry
+  %add4 = add nsw i32 %x, 2
+  br label %sw.epilog
+
+sw.bb5:                                           ; preds = %entry
+  %add6 = add nsw i32 %x, 3
+  br label %sw.epilog
+
+sw.epilog:                                        ; preds = %entry, %sw.bb5, %sw.bb3, %sw.bb2
+  %a.0 = phi i32 [ %add6, %sw.bb5 ], [ %add4, %sw.bb3 ], [ %add, %sw.bb2 ], [ %x, %entry ]
+  br label %for.cond.cleanup
+
+for.cond.cleanup:                                 ; preds = %sw.epilog, %entry
+  %a.028 = phi i32 [ %a.0, %sw.epilog ], [ 0, %entry ]
+  ret i32 %a.028
+}