Index: llvm/include/llvm/CodeGen/MachineInstr.h =================================================================== --- llvm/include/llvm/CodeGen/MachineInstr.h +++ llvm/include/llvm/CodeGen/MachineInstr.h @@ -1651,9 +1651,14 @@ /// Add all implicit def and use operands to this instruction. void addImplicitDefUseOperands(MachineFunction &MF); - /// Scan instructions following MI and collect any matching DBG_VALUEs. + /// Scan instructions immediately following MI and collect any matching + /// DBG_VALUEs. void collectDebugValues(SmallVectorImpl &DbgValues); + /// Scan the surrounding block for DBG_VALUEs of this instructions first + /// vreg argument. + void collectBlockDebugValues(SmallVectorImpl &DbgValues); + /// Find all DBG_VALUEs that point to the register def in this instruction /// and point them to \p Reg instead. void changeDebugValuesDefReg(Register Reg); Index: llvm/lib/CodeGen/CodeGenPrepare.cpp =================================================================== --- llvm/lib/CodeGen/CodeGenPrepare.cpp +++ llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -7205,28 +7205,30 @@ return MadeChange; } -// llvm.dbg.value is far away from the value then iSel may not be able -// handle it properly. iSel will drop llvm.dbg.value if it can not -// find a node corresponding to the value. +// A llvm.dbg.value may be using a value before its definition, due to +// optimizations in this pass and others. Scan for such dbg.values, and rescue +// them by moving the dbg.value to immediately after the value definition. +// FIXME: Ideally this should never be necessary, and this has the potential +// to re-order dbg.value intrinsics. bool CodeGenPrepare::placeDbgValues(Function &F) { bool MadeChange = false; + DominatorTree DT(F); + for (BasicBlock &BB : F) { - Instruction *PrevNonDbgInst = nullptr; for (BasicBlock::iterator BI = BB.begin(), BE = BB.end(); BI != BE;) { Instruction *Insn = &*BI++; DbgValueInst *DVI = dyn_cast(Insn); - // Leave dbg.values that refer to an alloca alone. These - // intrinsics describe the address of a variable (= the alloca) - // being taken. They should not be moved next to the alloca - // (and to the beginning of the scope), but rather stay close to - // where said address is used. - if (!DVI || (DVI->getValue() && isa(DVI->getValue()))) { - PrevNonDbgInst = Insn; + if (!DVI) continue; - } Instruction *VI = dyn_cast_or_null(DVI->getValue()); - if (VI && VI != PrevNonDbgInst && !VI->isTerminator()) { + + // If the defining instruction dominates the dbg.value, we do not need + // to move the dbg.value. + if (VI && DT.dominates(VI, DVI)) + continue; + + if (VI && !VI->isTerminator()) { // If VI is a phi in a block with an EHPad terminator, we can't insert // after it. if (isa(VI) && VI->getParent()->getTerminator()->isEHPad()) Index: llvm/lib/CodeGen/MachineInstr.cpp =================================================================== --- llvm/lib/CodeGen/MachineInstr.cpp +++ llvm/lib/CodeGen/MachineInstr.cpp @@ -2119,6 +2119,20 @@ } } +void MachineInstr::collectBlockDebugValues( + SmallVectorImpl &DbgValues) { + MachineInstr &MI = *this; + if (!MI.getOperand(0).isReg() || MI.getOperand(0).getReg() == 0) + return; + + auto &MRI = this->getParent()->getParent()->getRegInfo(); + + for (auto &UseMI : MRI.use_instructions(MI.getOperand(0).getReg())) { + if (UseMI.isDebugValue() && getParent() == UseMI.getParent()) + DbgValues.push_back(&UseMI); + } +} + void MachineInstr::changeDebugValuesDefReg(Register Reg) { // Collect matching debug values. SmallVector DbgValues; Index: llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.h +++ llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.h @@ -16,6 +16,7 @@ #define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYDEBUGVALUEMANAGER_H #include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/LiveIntervals.h" namespace llvm { @@ -25,7 +26,8 @@ SmallVector DbgValues; public: - WebAssemblyDebugValueManager(MachineInstr *Instr); + WebAssemblyDebugValueManager(unsigned OldReg, LiveIntervals &LIS, + MachineInstr *Instr); void move(MachineInstr *Insert); void updateReg(unsigned Reg); Index: llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp +++ llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp @@ -13,13 +13,40 @@ #include "WebAssemblyDebugValueManager.h" #include "WebAssemblyMachineFunctionInfo.h" +#include "llvm/CodeGen/LiveIntervals.h" #include "llvm/CodeGen/MachineInstr.h" using namespace llvm; WebAssemblyDebugValueManager::WebAssemblyDebugValueManager( - MachineInstr *Instr) { - Instr->collectDebugValues(DbgValues); + unsigned OldReg, LiveIntervals &LIS, MachineInstr *Instr) { + // Fetch nearby DBG_VALUEs referring to this instruction. + SmallVector TmpDbgValues; + Instr->collectBlockDebugValues(TmpDbgValues); + + const SlotIndexes &Slots = *LIS.getSlotIndexes(); + LiveInterval &LI = LIS.getInterval(OldReg); + + // Get the value number for this instructions register write. + SlotIndex ThisInstrSlot = Slots.getInstructionIndex(*Instr).getDeadSlot(); + LiveRange::Segment *InstrSeg = LI.find(ThisInstrSlot); + assert(InstrSeg != LI.end() && InstrSeg->start <= ThisInstrSlot && + "No value number for instr reg write?"); + unsigned InstrValNo = InstrSeg->valno->id; + + // Examine the collected DBG_VALUEs: if they refer to the same value number + // as this instruction defines, then store them. Otherwise, ignore them. + for (MachineInstr *DbgMI : TmpDbgValues) { + // Find an instruction that has a slot index. + MachineInstr *NextRealInst = &*skipDebugInstructionsForward( + DbgMI->getIterator(), DbgMI->getParent()->instr_end()); + SlotIndex Idx = Slots.getInstructionIndex(*NextRealInst); + + // Examine the value number at that slot. + LiveRange::Segment *Seg = LI.find(Idx); + if (Seg != LI.end() && Seg->start <= Idx && Seg->valno->id == InstrValNo) + DbgValues.push_back(DbgMI); + } } void WebAssemblyDebugValueManager::move(MachineInstr *Insert) { Index: llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp +++ llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp @@ -487,7 +487,7 @@ MachineRegisterInfo &MRI) { LLVM_DEBUG(dbgs() << "Move for single use: "; Def->dump()); - WebAssemblyDebugValueManager DefDIs(Def); + WebAssemblyDebugValueManager DefDIs(Reg, LIS, Def); MBB.splice(Insert, &MBB, Def); DefDIs.move(Insert); LIS.handleMove(*Def); @@ -533,7 +533,7 @@ LLVM_DEBUG(dbgs() << "Rematerializing cheap def: "; Def.dump()); LLVM_DEBUG(dbgs() << " - for use in "; Op.getParent()->dump()); - WebAssemblyDebugValueManager DefDIs(&Def); + WebAssemblyDebugValueManager DefDIs(Reg, LIS, &Def); Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg)); TII->reMaterialize(MBB, Insert, NewReg, 0, Def, *TRI); @@ -599,7 +599,7 @@ MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII) { LLVM_DEBUG(dbgs() << "Move and tee for multi-use:"; Def->dump()); - WebAssemblyDebugValueManager DefDIs(Def); + WebAssemblyDebugValueManager DefDIs(Reg, LIS, Def); // Move Def into place. MBB.splice(Insert, &MBB, Def); Index: llvm/test/DebugInfo/COFF/register-variables.ll =================================================================== --- llvm/test/DebugInfo/COFF/register-variables.ll +++ llvm/test/DebugInfo/COFF/register-variables.ll @@ -32,9 +32,6 @@ ; ASM: #DEBUG_VALUE: f:p <- $esi ; ASM: callq getint ; ASM: [[after_getint:\.Ltmp.*]]: -; ASM: #DEBUG_VALUE: a <- $eax -; ASM: #DEBUG_VALUE: inlineinc:a <- $eax -; ASM: #DEBUG_VALUE: c <- $eax ; ASM: testl %esi, %esi ; ASM: je .LBB0_2 ; ASM: [[after_je:\.Ltmp.*]]: @@ -45,16 +42,17 @@ ; ASM: addl $1, %eax ; ASM: [[after_inc_eax:\.Ltmp.*]]: ; ASM: #DEBUG_VALUE: inlineinc:b <- $eax -; ASM: #DEBUG_VALUE: b <- $eax ; ASM: addl $1, x(%rip) ; ASM: [[after_if:\.Ltmp.*]]: ; ASM: .LBB0_2: # %if.else ; ASM: #DEBUG_VALUE: f:p <- $esi +; ASM: #DEBUG_VALUE: c <- $eax ; ASM: movl %eax, %ecx ; ASM: addq $32, %rsp ; ASM: popq %rsi ; ASM: [[func_end:\.Ltmp.*]]: ; ASM: jmp putint # TAILCALL +; ASM: [[func_finished:\.Ltmp.*]]: ; ASM: .short 4414 # Record kind: S_LOCAL ; ASM: .asciz "p" @@ -62,18 +60,20 @@ ; ASM: .cv_def_range [[p_ecx_esi]] [[func_end]], reg, 23 ; ASM: .short 4414 # Record kind: S_LOCAL ; ASM: .asciz "c" -; ASM: .cv_def_range [[after_getint]] [[after_je]], reg, 17 +; ASM: .cv_def_range [[after_if]] [[func_finished]], reg, 17 ; ASM: .short 4414 # Record kind: S_LOCAL ; ASM: .asciz "a" -; ASM: .cv_def_range [[after_getint]] [[after_inc_eax]], reg, 17 +; ASM: .cv_def_range [[after_je]] [[after_inc_eax]], reg, 17 ; ASM: .short 4414 # Record kind: S_LOCAL ; ASM: .asciz "b" -; ASM: .cv_def_range [[after_inc_eax]] [[after_if]], reg, 17 +; ASM: .cv_def_range [[after_if]] [[after_if]], reg, 17 + +; Note: "b" is a victim of tail de-duplication / branch folding. ; ASM: .short 4429 # Record kind: S_INLINESITE ; ASM: .short 4414 # Record kind: S_LOCAL ; ASM: .asciz "a" -; ASM: .cv_def_range [[after_getint]] [[after_inc_eax]], reg, 17 +; ASM: .cv_def_range [[after_je]] [[after_inc_eax]], reg, 17 ; ASM: .short 4414 # Record kind: S_LOCAL ; ASM: .asciz "b" ; ASM: .cv_def_range [[after_inc_eax]] [[after_if]], reg, 17 @@ -116,9 +116,9 @@ ; OBJ: DefRangeRegisterSym { ; OBJ: Register: EAX (0x11) ; OBJ: LocalVariableAddrRange { -; OBJ: OffsetStart: .text+0xC +; OBJ: OffsetStart: .text+0x1A ; OBJ: ISectStart: 0x0 -; OBJ: Range: 0x4 +; OBJ: Range: 0xC ; OBJ: } ; OBJ: } ; OBJ: LocalSym { @@ -130,23 +130,9 @@ ; OBJ: DefRangeRegisterSym { ; OBJ: Register: EAX (0x11) ; OBJ: LocalVariableAddrRange { -; OBJ: OffsetStart: .text+0xC +; OBJ: OffsetStart: .text+0x10 ; OBJ: ISectStart: 0x0 -; OBJ: Range: 0x7 -; OBJ: } -; OBJ: } -; OBJ: LocalSym { -; OBJ: Type: int (0x74) -; OBJ: Flags [ (0x0) -; OBJ: ] -; OBJ: VarName: b -; OBJ: } -; OBJ: DefRangeRegisterSym { -; OBJ: Register: EAX (0x11) -; OBJ: MayHaveNoName: 0 -; OBJ: OffsetStart: .text+0x13 -; OBJ: ISectStart: 0x0 -; OBJ: Range: 0x7 +; OBJ: Range: 0x3 ; OBJ: } ; OBJ: } ; OBJ: InlineSiteSym { @@ -164,9 +150,9 @@ ; OBJ: DefRangeRegisterSym { ; OBJ: Register: EAX (0x11) ; OBJ: LocalVariableAddrRange { -; OBJ: OffsetStart: .text+0xC +; OBJ: OffsetStart: .text+0x10 ; OBJ: ISectStart: 0x0 -; OBJ: Range: 0x7 +; OBJ: Range: 0x3 ; OBJ: } ; OBJ: } ; OBJ: LocalSym { Index: llvm/test/DebugInfo/NVPTX/debug-info.ll =================================================================== --- llvm/test/DebugInfo/NVPTX/debug-info.ll +++ llvm/test/DebugInfo/NVPTX/debug-info.ll @@ -8388,8 +8388,8 @@ ; CHECK-NEXT: .b8 37 // DW_AT_call_column ; CHECK-NEXT: .b8 43 // Abbrev [43] 0x2711:0x23 DW_TAG_inlined_subroutine ; CHECK-NEXT: .b32 9791 // DW_AT_abstract_origin -; CHECK-NEXT: .b64 Ltmp10 // DW_AT_low_pc -; CHECK-NEXT: .b64 Ltmp11 // DW_AT_high_pc +; CHECK-NEXT: .b64 Ltmp9 // DW_AT_low_pc +; CHECK-NEXT: .b64 Ltmp10 // DW_AT_high_pc ; CHECK-NEXT: .b8 12 // DW_AT_call_file ; CHECK-NEXT: .b8 8 // DW_AT_call_line ; CHECK-NEXT: .b8 5 // DW_AT_call_column Index: llvm/test/DebugInfo/X86/DW_AT_location-reference.ll =================================================================== --- llvm/test/DebugInfo/X86/DW_AT_location-reference.ll +++ llvm/test/DebugInfo/X86/DW_AT_location-reference.ll @@ -32,7 +32,9 @@ ; CHECK: .debug_info contents: ; CHECK: DW_TAG_variable ; CHECK-NEXT: DW_AT_location [DW_FORM_sec_offset] (0x00000000 -; Check that the location contains only 2 ranges. +; Check that the location contains only 4 ranges. +; CHECK-NEXT: [0x{{[0-9a-f]*}}, 0x{{[0-9a-f]*}}) +; CHECK-NEXT: [0x{{[0-9a-f]*}}, 0x{{[0-9a-f]*}}) ; CHECK-NEXT: [0x{{[0-9a-f]*}}, 0x{{[0-9a-f]*}}) ; CHECK-NEXT: [0x{{[0-9a-f]*}}, 0x{{[0-9a-f]*}}){{.*}}) ; CHECK-NEXT: DW_AT_name {{.*}} "x" Index: llvm/test/DebugInfo/X86/PR37234.ll =================================================================== --- llvm/test/DebugInfo/X86/PR37234.ll +++ llvm/test/DebugInfo/X86/PR37234.ll @@ -20,9 +20,8 @@ ; CHECK-LABEL: # %bb.{{.*}}: ; CHECK: #DEBUG_VALUE: main:aa <- 0 -; CHECK: #DEBUG_VALUE: main:aa <- $[[REG:[0-9a-z]+]] ; CHECK: .LBB0_1: -; CHECK: #DEBUG_VALUE: main:aa <- $[[REG]] +; CHECK: #DEBUG_VALUE: main:aa <- $[[REG:[0-9a-z]+]] ; CHECK: je .LBB0_4 ; CHECK: # %bb.{{.*}}: ; CHECK: #DEBUG_VALUE: main:aa <- $[[REG]] Index: llvm/test/tools/llvm-locstats/locstats.ll =================================================================== --- llvm/test/tools/llvm-locstats/locstats.ll +++ llvm/test/tools/llvm-locstats/locstats.ll @@ -11,9 +11,9 @@ ; LOCSTATS: 30-39% 0 0% ; LOCSTATS: 40-49% 1 11% ; LOCSTATS: 50-59% 1 11% -; LOCSTATS: 60-69% 1 11% +; LOCSTATS: 60-69% 0 0% ; LOCSTATS: 70-79% 0 0% -; LOCSTATS: 80-89% 2 22% +; LOCSTATS: 80-89% 3 33% ; LOCSTATS: 90-99% 1 11% ; LOCSTATS: 100% 2 22% ;