Index: lib/Target/X86/X86DiscriminateMemOps.cpp =================================================================== --- lib/Target/X86/X86DiscriminateMemOps.cpp +++ lib/Target/X86/X86DiscriminateMemOps.cpp @@ -85,7 +85,7 @@ // have any debug info. const DILocation *ReferenceDI = DILocation::get(FDI->getContext(), FDI->getLine(), 0, FDI); - + assert(ReferenceDI && "ReferenceDI should not be nullptr"); DenseMap MemOpDiscriminators; MemOpDiscriminators[diToLocation(ReferenceDI)] = 0; @@ -143,6 +143,7 @@ // Since we were able to encode, bump the MemOpDiscriminators. ++MemOpDiscriminators[L]; DI = DI->cloneWithDiscriminator(EncodedDiscriminator.getValue()); + assert(DI && "DI should not be nullptr"); updateDebugInfo(&MI, DI); Changed = true; std::pair::iterator, bool> MustInsert = Index: lib/Target/X86/X86InstructionSelector.cpp =================================================================== --- lib/Target/X86/X86InstructionSelector.cpp +++ lib/Target/X86/X86InstructionSelector.cpp @@ -1600,8 +1600,8 @@ assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) && "Arguments and return value types must match"); - const RegisterBank &RegRB = *RBI.getRegBank(DstReg, MRI, TRI); - if (RegRB.getID() != X86::GPRRegBankID) + const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI); + if (!RegRB || RegRB->getID() != X86::GPRRegBankID) return false; const static unsigned NumTypes = 4; // i8, i16, i32, i64 @@ -1699,7 +1699,7 @@ const DivRemEntry &TypeEntry = *OpEntryIt; const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; - const TargetRegisterClass *RegRC = getRegClass(RegTy, RegRB); + const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB); if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) || !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) || !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) {