Index: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -173,6 +173,7 @@ ImmTyNegLo, ImmTyNegHi, ImmTySwizzle, + ImmTyGprIdxMode, ImmTyHigh }; @@ -694,6 +695,7 @@ case ImmTyNegLo: OS << "NegLo"; break; case ImmTyNegHi: OS << "NegHi"; break; case ImmTySwizzle: OS << "Swizzle"; break; + case ImmTyGprIdxMode: OS << "GprIdxMode"; break; case ImmTyHigh: OS << "High"; break; } } @@ -1129,6 +1131,9 @@ bool parseSwizzleSwap(int64_t &Imm); bool parseSwizzleReverse(int64_t &Imm); + OperandMatchResultTy parseGPRIdxMode(OperandVector &Operands); + int64_t parseGPRIdxMacro(); + void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false); } void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, false); } void cvtMubufAtomicReturn(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, true); } @@ -4649,6 +4654,88 @@ } //===----------------------------------------------------------------------===// +// VGPR Index Mode +//===----------------------------------------------------------------------===// + +int64_t AMDGPUAsmParser::parseGPRIdxMacro() { + + using namespace llvm::AMDGPU::VGPRIndexMode; + + if (trySkipToken(AsmToken::RParen)) { + return OFF; + } + + int64_t Imm = 0; + + while (true) { + unsigned Mode = 0; + SMLoc S = Parser.getTok().getLoc(); + + for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) { + if (trySkipId(IdSymbolic[ModeId])) { + Mode = 1 << ModeId; + break; + } + } + + if (Mode == 0) { + Error(S, (Imm == 0)? + "expected a VGPR index mode or a closing parenthesis" : + "expected a VGPR index mode"); + break; + } + + if (Imm & Mode) { + Error(S, "duplicate VGPR index mode"); + break; + } + Imm |= Mode; + + if (trySkipToken(AsmToken::RParen)) + break; + if (!skipToken(AsmToken::Comma, + "expected a comma or a closing parenthesis")) + break; + } + + return Imm; +} + +OperandMatchResultTy +AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) { + + int64_t Imm = 0; + SMLoc S = Parser.getTok().getLoc(); + + if (getLexer().getKind() == AsmToken::Identifier && + Parser.getTok().getString() == "gpr_idx" && + getLexer().peekTok().is(AsmToken::LParen)) { + + Parser.Lex(); + Parser.Lex(); + + // If parse failed, trigger an error but do not return error code + // to avoid excessive error messages. + Imm = parseGPRIdxMacro(); + + } else { + if (getParser().parseAbsoluteExpression(Imm)) + return MatchOperand_NoMatch; + if (Imm < 0 || !isUInt<4>(Imm)) { + Error(S, "invalid immediate: only 4-bit values are legal"); + } + } + + Operands.push_back( + AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTyGprIdxMode)); + return MatchOperand_Success; +} + +bool AMDGPUOperand::isGPRIdxMode() const { + return isImmTy(ImmTyGprIdxMode); +} + +//===----------------------------------------------------------------------===// // sopp branch targets //===----------------------------------------------------------------------===// @@ -5289,10 +5376,6 @@ return false; } -bool AMDGPUOperand::isGPRIdxMode() const { - return isImm() && isUInt<4>(getImm()); -} - bool AMDGPUOperand::isS16Imm() const { return isImm() && (isInt<16>(getImm()) || isUInt<16>(getImm())); } Index: llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp +++ llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp @@ -934,23 +934,24 @@ void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { + using namespace llvm::AMDGPU::VGPRIndexMode; unsigned Val = MI->getOperand(OpNo).getImm(); - if (Val == 0) { - O << " 0"; - return; - } - - if (Val & VGPRIndexMode::DST_ENABLE) - O << " dst"; - - if (Val & VGPRIndexMode::SRC0_ENABLE) - O << " src0"; - - if (Val & VGPRIndexMode::SRC1_ENABLE) - O << " src1"; - if (Val & VGPRIndexMode::SRC2_ENABLE) - O << " src2"; + if ((Val & ~ENABLE_MASK) != 0) { + O << " " << formatHex(static_cast(Val)); + } else { + O << " gpr_idx("; + bool NeedComma = false; + for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) { + if (Val & (1 << ModeId)) { + if (NeedComma) + O << ','; + O << IdSymbolic[ModeId]; + NeedComma = true; + } + } + O << ')'; + } } void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, Index: llvm/trunk/lib/Target/AMDGPU/SIDefines.h =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIDefines.h +++ llvm/trunk/lib/Target/AMDGPU/SIDefines.h @@ -180,14 +180,30 @@ }; } +namespace AMDGPU { namespace VGPRIndexMode { - enum { - SRC0_ENABLE = 1 << 0, - SRC1_ENABLE = 1 << 1, - SRC2_ENABLE = 1 << 2, - DST_ENABLE = 1 << 3 - }; -} + +enum Id { // id of symbolic names + ID_SRC0 = 0, + ID_SRC1, + ID_SRC2, + ID_DST, + + ID_MIN = ID_SRC0, + ID_MAX = ID_DST +}; + +enum EncBits { + OFF = 0, + SRC0_ENABLE = 1 << ID_SRC0, + SRC1_ENABLE = 1 << ID_SRC1, + SRC2_ENABLE = 1 << ID_SRC2, + DST_ENABLE = 1 << ID_DST, + ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE +}; + +} // namespace VGPRIndexMode +} // namespace AMDGPU namespace AMDGPUAsmVariants { enum { Index: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp @@ -2911,7 +2911,7 @@ .addImm(Offset); } unsigned IdxMode = IsIndirectSrc ? - VGPRIndexMode::SRC0_ENABLE : VGPRIndexMode::DST_ENABLE; + AMDGPU::VGPRIndexMode::SRC0_ENABLE : AMDGPU::VGPRIndexMode::DST_ENABLE; MachineInstr *SetOn = BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON)) .addReg(IdxReg, RegState::Kill) @@ -3042,7 +3042,7 @@ if (UseGPRIdxMode) { unsigned IdxMode = IsIndirectSrc ? - VGPRIndexMode::SRC0_ENABLE : VGPRIndexMode::DST_ENABLE; + AMDGPU::VGPRIndexMode::SRC0_ENABLE : AMDGPU::VGPRIndexMode::DST_ENABLE; if (Offset == 0) { MachineInstr *SetOn = BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON)) Index: llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td +++ llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td @@ -9,6 +9,7 @@ def GPRIdxModeMatchClass : AsmOperandClass { let Name = "GPRIdxMode"; let PredicateMethod = "isGPRIdxMode"; + let ParserMethod = "parseGPRIdxMode"; let RenderMethod = "addImmOperands"; } Index: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h =================================================================== --- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h +++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h @@ -30,6 +30,13 @@ extern const char* const IdSymbolic[]; } // namespace Swizzle + +namespace VGPRIndexMode { // Symbolic names for the gpr_idx(...) syntax. + +extern const char* const IdSymbolic[]; + +} // namespace VGPRIndexMode + } // namespace AMDGPU } // namespace llvm Index: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp +++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp @@ -85,5 +85,18 @@ }; } // namespace Swizzle + +namespace VGPRIndexMode { + +// This must be in sync with llvm::AMDGPU::VGPRIndexMode::Id enum members, see SIDefines.h. +const char* const IdSymbolic[] = { + "SRC0", + "SRC1", + "SRC2", + "DST", +}; + +} // namespace VGPRIndexMode + } // namespace AMDGPU } // namespace llvm Index: llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll +++ llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll @@ -24,7 +24,7 @@ ; MOVREL: s_mov_b32 m0, [[READLANE]] ; MOVREL-NEXT: v_movreld_b32_e32 v[[VEC_ELT0]], [[INS0]] -; IDXMODE: s_set_gpr_idx_on [[READLANE]], dst +; IDXMODE: s_set_gpr_idx_on [[READLANE]], gpr_idx(DST) ; IDXMODE-NEXT: v_mov_b32_e32 v[[VEC_ELT0]], [[INS0]] ; IDXMODE: s_set_gpr_idx_off @@ -44,7 +44,7 @@ ; MOVREL: s_mov_b32 m0, [[READLANE]] ; MOVREL-NEXT: v_movreld_b32_e32 v{{[0-9]+}}, 63 -; IDXMODE: s_set_gpr_idx_on [[READLANE]], dst +; IDXMODE: s_set_gpr_idx_on [[READLANE]], gpr_idx(DST) ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, 63 ; IDXMODE: s_set_gpr_idx_off Index: llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si-pregfx9.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si-pregfx9.ll +++ llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si-pregfx9.ll @@ -27,7 +27,7 @@ ; MOVREL: s_mov_b32 m0, [[READLANE]] ; MOVREL-NEXT: v_movreld_b32_e32 v[[VEC_ELT0]], [[INS0]] -; IDXMODE: s_set_gpr_idx_on [[READLANE]], dst +; IDXMODE: s_set_gpr_idx_on [[READLANE]], gpr_idx(DST) ; IDXMODE-NEXT: v_mov_b32_e32 v[[VEC_ELT0]], [[INS0]] ; IDXMODE: s_set_gpr_idx_off @@ -47,7 +47,7 @@ ; MOVREL: s_mov_b32 m0, [[READLANE]] ; MOVREL-NEXT: v_movreld_b32_e32 v{{[0-9]+}}, 63 -; IDXMODE: s_set_gpr_idx_on [[READLANE]], dst +; IDXMODE: s_set_gpr_idx_on [[READLANE]], gpr_idx(DST) ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, 63 ; IDXMODE: s_set_gpr_idx_off Index: llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll +++ llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll @@ -17,7 +17,7 @@ ; MOVREL-DAG: s_mov_b32 m0, [[IN]] ; MOVREL: v_movrels_b32_e32 v{{[0-9]+}}, [[BASEREG]] -; IDXMODE: s_set_gpr_idx_on [[IN]], src0{{$}} +; IDXMODE: s_set_gpr_idx_on [[IN]], gpr_idx(SRC0){{$}} ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, [[BASEREG]] ; IDXMODE-NEXT: s_set_gpr_idx_off define amdgpu_kernel void @extract_w_offset(float addrspace(1)* %out, i32 %in) { @@ -43,7 +43,7 @@ ; MOVREL: v_movrels_b32_e32 -; IDXMODE: s_set_gpr_idx_on s{{[0-9]+}}, src0{{$}} +; IDXMODE: s_set_gpr_idx_on s{{[0-9]+}}, gpr_idx(SRC0){{$}} ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} ; IDXMODE-NEXT: s_set_gpr_idx_off define amdgpu_kernel void @extract_w_offset_salu_use_vector(i32 addrspace(1)* %out, i32 %in, <16 x i32> %or.val) { @@ -65,7 +65,7 @@ ; MOVREL-DAG: s_mov_b32 m0, [[IN]] ; MOVREL: v_movrels_b32_e32 v{{[0-9]+}}, [[BASEREG]] -; IDXMODE: s_set_gpr_idx_on [[IN]], src0{{$}} +; IDXMODE: s_set_gpr_idx_on [[IN]], gpr_idx(SRC0){{$}} ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, [[BASEREG]] ; IDXMODE-NEXT: s_set_gpr_idx_off define amdgpu_kernel void @extract_wo_offset(float addrspace(1)* %out, i32 %in) { @@ -83,7 +83,7 @@ ; IDXMODE: s_addk_i32 [[ADD_IDX:s[0-9]+]], 0xfe00{{$}} ; IDXMODE: v_mov_b32_e32 v14, 15 ; IDXMODE: v_mov_b32_e32 v15, 16 -; IDXMODE-NEXT: s_set_gpr_idx_on [[ADD_IDX]], src0{{$}} +; IDXMODE-NEXT: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(SRC0){{$}} ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} ; IDXMODE-NEXT: s_set_gpr_idx_off define amdgpu_kernel void @extract_neg_offset_sgpr(i32 addrspace(1)* %out, i32 %offset) { @@ -116,7 +116,7 @@ ; IDXMODE: v_mov_b32_e32 v13, ; IDXMODE: v_mov_b32_e32 v14, ; IDXMODE: v_mov_b32_e32 v15, -; IDXMODE-NEXT: s_set_gpr_idx_on [[ADD_IDX]], src0{{$}} +; IDXMODE-NEXT: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(SRC0){{$}} ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} ; IDXMODE-NEXT: s_set_gpr_idx_off define amdgpu_kernel void @extract_neg_offset_sgpr_loaded(i32 addrspace(1)* %out, <16 x i32> %vec0, <16 x i32> %vec1, i32 %offset) { @@ -141,7 +141,7 @@ ; MOVREL: v_movrels_b32_e32 [[RESULT:v[0-9]+]], v1 ; IDXMODE: s_addk_i32 [[ADD_IDX:s[0-9]+]], 0xfe00 -; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], src0 +; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(SRC0) ; IDXMODE: v_mov_b32_e32 [[RESULT:v[0-9]+]], v1 ; IDXMODE: s_set_gpr_idx_off @@ -207,7 +207,7 @@ ; MOVREL: s_mov_b32 m0, [[BASE]] ; MOVREL: v_movreld_b32_e32 [[ELT1]], v{{[0-9]+}} -; IDXMODE: s_set_gpr_idx_on [[BASE]], dst +; IDXMODE: s_set_gpr_idx_on [[BASE]], gpr_idx(DST) ; IDXMODE-NEXT: v_mov_b32_e32 [[ELT1]], v{{[0-9]+}} ; IDXMODE-NEXT: s_set_gpr_idx_off define amdgpu_kernel void @insert_unsigned_base_plus_offset(<16 x float> addrspace(1)* %out, i16 %in) { @@ -230,7 +230,7 @@ ; MOVREL: s_mov_b32 m0, [[BASE_PLUS_OFFSET]] ; MOVREL: v_movreld_b32_e32 [[ELT0]], v{{[0-9]+}} -; IDXMODE: s_set_gpr_idx_on [[BASE_PLUS_OFFSET]], dst +; IDXMODE: s_set_gpr_idx_on [[BASE_PLUS_OFFSET]], gpr_idx(DST) ; IDXMODE-NEXT: v_mov_b32_e32 [[ELT0]], v{{[0-9]+}} ; IDXMODE-NEXT: s_set_gpr_idx_off define amdgpu_kernel void @insert_signed_base_plus_offset(<16 x float> addrspace(1)* %out, i16 %in) { @@ -249,7 +249,7 @@ ; MOVREL: s_mov_b32 m0, [[IN]] ; MOVREL: v_movreld_b32_e32 v[[ELT0:[0-9]+]] -; IDXMODE: s_set_gpr_idx_on [[IN]], dst +; IDXMODE: s_set_gpr_idx_on [[IN]], gpr_idx(DST) ; IDXMODE-NEXT: v_mov_b32_e32 v[[ELT0:[0-9]+]], v{{[0-9]+}} ; IDXMODE-NEXT: s_set_gpr_idx_off @@ -267,7 +267,7 @@ ; MOVREL: v_movreld_b32_e32 v0, 16 ; IDXMODE: s_addk_i32 [[ADD_IDX:s[0-9]+]], 0xfe00{{$}} -; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], dst +; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(DST) ; IDXMODE-NEXT: v_mov_b32_e32 v0, 16 ; IDXMODE-NEXT: s_set_gpr_idx_off define amdgpu_kernel void @insert_neg_offset_sgpr(i32 addrspace(1)* %in, <16 x i32> addrspace(1)* %out, i32 %offset) { @@ -287,7 +287,7 @@ ; MOVREL: v_movreld_b32_e32 v0, 5 ; IDXMODE: s_addk_i32 [[ADD_IDX:s[0-9]+]], 0xfe00{{$}} -; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], dst +; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(DST) ; IDXMODE-NEXT: v_mov_b32_e32 v0, 5 ; IDXMODE-NEXT: s_set_gpr_idx_off define amdgpu_kernel void @insert_neg_offset_sgpr_loadreg(i32 addrspace(1)* %in, <16 x i32> addrspace(1)* %out, <16 x i32> %vec, i32 %offset) { @@ -327,7 +327,7 @@ ; MOVREL: v_movreld_b32_e32 [[VEC_ELT0]], 33 ; IDXMODE: s_addk_i32 [[ADD_IDX:s[0-9]+]], 0xfe00{{$}} -; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], dst +; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(DST) ; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, 33 ; IDXMODE: s_set_gpr_idx_off @@ -373,7 +373,7 @@ ; MOVREL: v_movreld_b32_e32 [[VEC_ELT0]], [[VAL]] ; IDXMODE: s_add_i32 [[ADD_IDX:s[0-9]+]], [[READLANE]], -16 -; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], dst +; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(DST) ; IDXMODE: v_mov_b32_e32 [[VEC_ELT0]], [[VAL]] ; IDXMODE: s_set_gpr_idx_off @@ -415,7 +415,7 @@ ; MOVREL: s_mov_b32 m0, [[READLANE]] ; MOVREL: v_movrels_b32_e32 [[MOVREL0:v[0-9]+]], [[VEC_ELT0]] -; IDXMODE: s_set_gpr_idx_on [[READLANE]], src0 +; IDXMODE: s_set_gpr_idx_on [[READLANE]], gpr_idx(SRC0) ; IDXMODE: v_mov_b32_e32 [[MOVREL0:v[0-9]+]], [[VEC_ELT0]] ; IDXMODE: s_set_gpr_idx_off @@ -437,7 +437,7 @@ ; MOVREL: s_mov_b32 m0, [[READLANE]] ; MOVREL-NEXT: v_movrels_b32_e32 [[MOVREL1:v[0-9]+]], [[VEC_ELT0_2]] -; IDXMODE: s_set_gpr_idx_on [[READLANE]], src0 +; IDXMODE: s_set_gpr_idx_on [[READLANE]], gpr_idx(SRC0) ; IDXMODE-NEXT: v_mov_b32_e32 [[MOVREL1:v[0-9]+]], [[VEC_ELT0_2]] ; IDXMODE: s_set_gpr_idx_off @@ -516,11 +516,11 @@ ; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, 0x41900000 ; IDXMODE: s_waitcnt ; IDXMODE: s_add_i32 [[ARG]], [[ARG]], -16 -; IDXMODE: s_set_gpr_idx_on [[ARG]], dst +; IDXMODE: s_set_gpr_idx_on [[ARG]], gpr_idx(DST) ; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, 4.0 ; IDXMODE: s_set_gpr_idx_off ; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, 0x41b0cccd -; IDXMODE: s_set_gpr_idx_on [[ARG]], dst +; IDXMODE: s_set_gpr_idx_on [[ARG]], gpr_idx(DST) ; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, -4.0 ; IDXMODE: s_set_gpr_idx_off @@ -551,7 +551,7 @@ ; MOVREL: s_mov_b32 m0, [[IDX]] ; MOVREL: v_movrels_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]] -; IDXMODE: s_set_gpr_idx_on [[IDX]], src0 +; IDXMODE: s_set_gpr_idx_on [[IDX]], gpr_idx(SRC0) ; IDXMODE: v_mov_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]] ; IDXMODE: s_set_gpr_idx_off @@ -573,7 +573,7 @@ ; MOVREL: s_mov_b32 m0, [[ADD_IDX]] ; MOVREL: v_movrels_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]] -; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], src0 +; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(SRC0) ; IDXMODE: v_mov_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]] ; IDXMODE: s_set_gpr_idx_off @@ -595,7 +595,7 @@ ; MOVREL: s_mov_b32 m0, [[IDX_FIN]] ; MOVREL: v_movrels_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} -; IDXMODE: s_set_gpr_idx_on [[IDX_FIN]], src0 +; IDXMODE: s_set_gpr_idx_on [[IDX_FIN]], gpr_idx(SRC0) ; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} ; IDXMODE: s_set_gpr_idx_off define amdgpu_kernel void @extractelement_v16i32_or_index(i32 addrspace(1)* %out, <16 x i32> addrspace(1)* %in, i32 %idx.in) { @@ -616,7 +616,7 @@ ; MOVREL: s_mov_b32 m0, [[IDX_FIN]] ; MOVREL: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} -; IDXMODE: s_set_gpr_idx_on [[IDX_FIN]], dst +; IDXMODE: s_set_gpr_idx_on [[IDX_FIN]], gpr_idx(DST) ; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} ; IDXMODE: s_set_gpr_idx_off define amdgpu_kernel void @insertelement_v16f32_or_index(<16 x float> addrspace(1)* %out, <16 x float> %a, i32 %idx.in) nounwind { Index: llvm/trunk/test/MC/AMDGPU/sopc-err.s =================================================================== --- llvm/trunk/test/MC/AMDGPU/sopc-err.s +++ llvm/trunk/test/MC/AMDGPU/sopc-err.s @@ -1,13 +1,31 @@ // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s s_set_gpr_idx_on s0, s1 -// GCN: error: invalid operand for instruction +// VI: error: expected absolute expression s_set_gpr_idx_on s0, 16 -// GCN: error: invalid operand for instruction +// VI: error: invalid immediate: only 4-bit values are legal s_set_gpr_idx_on s0, -1 -// GCN: error: invalid operand for instruction +// VI: error: invalid immediate: only 4-bit values are legal + +s_set_gpr_idx_on s0, gpr_idx +// VI: error: expected absolute expression + +s_set_gpr_idx_on s0, gpr_idx( +// VI: error: expected a VGPR index mode or a closing parenthesis + +s_set_gpr_idx_on s0, gpr_idx(X) +// VI: error: expected a VGPR index mode + +s_set_gpr_idx_on s0, gpr_idx(SRC0,DST,SRC1,DST) +// VI: error: duplicate VGPR index mode + +s_set_gpr_idx_on s0, gpr_idx(DST +// VI: error: expected a comma or a closing parenthesis + +s_set_gpr_idx_on s0, gpr_idx(SRC0, +// VI: error: expected a VGPR index mode s_cmp_eq_i32 0x12345678, 0x12345679 // GCN: error: only one literal operand is allowed Index: llvm/trunk/test/MC/AMDGPU/sopc.s =================================================================== --- llvm/trunk/test/MC/AMDGPU/sopc.s +++ llvm/trunk/test/MC/AMDGPU/sopc.s @@ -71,18 +71,44 @@ // VI: s_cmp_lg_u64 s[0:1], s[2:3] ; encoding: [0x00,0x02,0x13,0xbf] // NOSICI: error: instruction not supported on this GPU +gpr_idx = 1 +s_set_gpr_idx_on s0, gpr_idx +// VI: s_set_gpr_idx_on s0, gpr_idx(SRC0) ; encoding: [0x00,0x01,0x11,0xbf] +// NOSICI: error: + +gpr_idx_mode = 10 +s_set_gpr_idx_on s0, gpr_idx_mode + 5 +// VI: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x00,0x0f,0x11,0xbf] +// NOSICI: error: + s_set_gpr_idx_on s0, 0 -// VI: s_set_gpr_idx_on s0, 0 ; encoding: [0x00,0x00,0x11,0xbf] -// NOSICI: error: instruction not supported on this GPU +// VI: s_set_gpr_idx_on s0, gpr_idx() ; encoding: [0x00,0x00,0x11,0xbf] +// NOSICI: error: + +s_set_gpr_idx_on s0, gpr_idx() +// VI: s_set_gpr_idx_on s0, gpr_idx() ; encoding: [0x00,0x00,0x11,0xbf] +// NOSICI: error: s_set_gpr_idx_on s0, 1 -// VI: s_set_gpr_idx_on s0, src0 ; encoding: [0x00,0x01,0x11,0xbf] -// NOSICI: error: instruction not supported on this GPU +// VI: s_set_gpr_idx_on s0, gpr_idx(SRC0) ; encoding: [0x00,0x01,0x11,0xbf] +// NOSICI: error: + +s_set_gpr_idx_on s0, gpr_idx(SRC0) +// VI: s_set_gpr_idx_on s0, gpr_idx(SRC0) ; encoding: [0x00,0x01,0x11,0xbf] +// NOSICI: error: s_set_gpr_idx_on s0, 3 -// VI: s_set_gpr_idx_on s0, src0 src1 ; encoding: [0x00,0x03,0x11,0xbf] -// NOSICI: error: instruction not supported on this GPU +// VI: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1) ; encoding: [0x00,0x03,0x11,0xbf] +// NOSICI: error: + +s_set_gpr_idx_on s0, gpr_idx(SRC1,SRC0) +// VI: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1) ; encoding: [0x00,0x03,0x11,0xbf] +// NOSICI: error: s_set_gpr_idx_on s0, 15 -// VI: s_set_gpr_idx_on s0, dst src0 src1 src2 ; encoding: [0x00,0x0f,0x11,0xbf] -// NOSICI: error: instruction not supported on this GPU +// VI: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x00,0x0f,0x11,0xbf] +// NOSICI: error: + +s_set_gpr_idx_on s0, gpr_idx(SRC0,DST,SRC2,SRC1) +// VI: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x00,0x0f,0x11,0xbf] +// NOSICI: error: Index: llvm/trunk/test/MC/AMDGPU/sopp.s =================================================================== --- llvm/trunk/test/MC/AMDGPU/sopp.s +++ llvm/trunk/test/MC/AMDGPU/sopp.s @@ -232,15 +232,23 @@ s_set_gpr_idx_off // VI: s_set_gpr_idx_off ; encoding: [0x00,0x00,0x9c,0xbf] -// NOSICI: error: instruction not supported on this GPU +// NOSICI: error: s_set_gpr_idx_mode 0 -// VI: s_set_gpr_idx_mode 0 ; encoding: [0x00,0x00,0x9d,0xbf] -// NOSICI: error: instruction not supported on this GPU +// VI: s_set_gpr_idx_mode gpr_idx() ; encoding: [0x00,0x00,0x9d,0xbf] +// NOSICI: error: + +s_set_gpr_idx_mode gpr_idx() +// VI: s_set_gpr_idx_mode gpr_idx() ; encoding: [0x00,0x00,0x9d,0xbf] +// NOSICI: error: s_set_gpr_idx_mode 15 -// VI: s_set_gpr_idx_mode dst src0 src1 src2 ; encoding: [0x0f,0x00,0x9d,0xbf] -// NOSICI: error: instruction not supported on this GPU +// VI: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf] +// NOSICI: error: + +s_set_gpr_idx_mode gpr_idx(SRC2,SRC1,SRC0,DST) +// VI: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf] +// NOSICI: error: s_endpgm_saved // VI: s_endpgm_saved ; encoding: [0x00,0x00,0x9b,0xbf] Index: llvm/trunk/test/MC/Disassembler/AMDGPU/sopc_vi.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/AMDGPU/sopc_vi.txt +++ llvm/trunk/test/MC/Disassembler/AMDGPU/sopc_vi.txt @@ -53,3 +53,15 @@ # GCN: s_bitcmp0_b32 0xafaaffff, 0xafaaffff ; encoding: [0xff,0xff,0x0c,0xbf,0xff,0xff,0xaa,0xaf] 0xff 0xff 0x0c 0xbf 0xff 0xff 0xaa 0xaf + +# GCN: s_set_gpr_idx_on s0, gpr_idx(SRC0) ; encoding: [0x00,0x01,0x11,0xbf] +0x00,0x01,0x11,0xbf + +# GCN: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x00,0x0f,0x11,0xbf] +0x00,0x0f,0x11,0xbf + +# GCN: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x00,0x0f,0x11,0xbf] +0x00,0x0f,0x11,0xbf + +# GCN: s_set_gpr_idx_on s0, 0xff ; encoding: [0x00,0xff,0x11,0xbf] +0x00,0xff,0x11,0xbf Index: llvm/trunk/test/MC/Disassembler/AMDGPU/sopp_vi.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/AMDGPU/sopp_vi.txt +++ llvm/trunk/test/MC/Disassembler/AMDGPU/sopp_vi.txt @@ -125,3 +125,9 @@ # GCN: s_ttracedata ; encoding: [0x00,0x00,0x96,0xbf] 0x00 0x00 0x96 0xbf + +# GCN: s_set_gpr_idx_mode gpr_idx() ; encoding: [0x00,0x00,0x9d,0xbf] +0x00,0x00,0x9d,0xbf + +# GCN: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf] +0x0f,0x00,0x9d,0xbf