Index: lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
--- lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2691,6 +2691,17 @@
   case ARM::tSUBi3:
   case ARM::tSUBi8:
   case ARM::tMUL:
+  case ARM::tADC:
+  case ARM::tSBC:
+  case ARM::tRSB:
+  case ARM::tAND:
+  case ARM::tORR:
+  case ARM::tEOR:
+  case ARM::tBIC:
+  case ARM::tMVN:
+  case ARM::tASRri:
+  case ARM::tASRrr:
+  case ARM::tROR:
     IsThumb1 = true;
     LLVM_FALLTHROUGH;
   case ARM::RSBrr:
@@ -2813,20 +2824,22 @@
   // CMP. This peephole works on the vregs, so is still in SSA form. As a
   // consequence, the movs won't redefine/kill the MUL operands which would
   // make this reordering illegal.
+  const TargetRegisterInfo *TRI = &getRegisterInfo();
   if (MI && IsThumb1) {
     --I;
-    bool CanReorder = true;
-    const bool HasStmts = I != E;
-    for (; I != E; --I) {
-      if (I->getOpcode() != ARM::tMOVi8) {
-        CanReorder = false;
-        break;
+    if (I != E && !MI->readsRegister(ARM::CPSR, TRI)) {
+      bool CanReorder = true;
+      for (; I != E; --I) {
+        if (I->getOpcode() != ARM::tMOVi8) {
+          CanReorder = false;
+          break;
+        }
+      }
+      if (CanReorder) {
+        MI = MI->removeFromParent();
+        E = CmpInstr;
+        CmpInstr.getParent()->insert(E, MI);
       }
-    }
-    if (HasStmts && CanReorder) {
-      MI = MI->removeFromParent();
-      E = CmpInstr;
-      CmpInstr.getParent()->insert(E, MI);
     }
     I = CmpInstr;
     E = MI;
@@ -2834,7 +2847,6 @@
 
   // Check that CPSR isn't set between the comparison instruction and the one we
   // want to change. At the same time, search for SubAdd.
-  const TargetRegisterInfo *TRI = &getRegisterInfo();
   bool SubAddIsThumb1 = false;
   do {
     const MachineInstr &Instr = *--I;
Index: test/CodeGen/ARM/arm-and-tst-peephole.ll
===================================================================
--- test/CodeGen/ARM/arm-and-tst-peephole.ll
+++ test/CodeGen/ARM/arm-and-tst-peephole.ll
@@ -29,7 +29,6 @@
 
 ; THUMB:      movs r[[R0:[0-9]+]], #3
 ; THUMB-NEXT: ands r[[R0]], r
-; THUMB-NEXT: cmp r[[R0]], #0
 ; THUMB-NEXT: beq
 
 ; T2:      ands {{r[0-9]+}}, {{r[0-9]+}}, #3
Index: test/CodeGen/Thumb/peephole-mi.mir
===================================================================
--- test/CodeGen/Thumb/peephole-mi.mir
+++ test/CodeGen/Thumb/peephole-mi.mir
@@ -27,8 +27,7 @@
   ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
   ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
   ; CHECK:   [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg
-  ; CHECK:   [[tADC:%[0-9]+]]:tgpr, dead $cpsr = tADC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr
-  ; CHECK:   tCMPi8 [[tADC]], 0, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   [[tADC:%[0-9]+]]:tgpr, $cpsr = tADC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr
   ; CHECK:   tBcc %bb.2, 1, $cpsr
   ; CHECK:   tB %bb.1, 14, $noreg
   bb.0:
@@ -99,8 +98,7 @@
   ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
   ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
   ; CHECK:   [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg
-  ; CHECK:   [[tSBC:%[0-9]+]]:tgpr, dead $cpsr = tSBC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr
-  ; CHECK:   tCMPi8 [[tSBC]], 0, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   [[tSBC:%[0-9]+]]:tgpr, $cpsr = tSBC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr
   ; CHECK:   tBcc %bb.2, 1, $cpsr
   ; CHECK:   tB %bb.1, 14, $noreg
   bb.0:
@@ -131,8 +129,7 @@
 body:             |
   ; CHECK-LABEL: name: test_rsb
   ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r0
-  ; CHECK:   [[tRSB:%[0-9]+]]:tgpr, dead $cpsr = tRSB [[COPY]], 14, $noreg
-  ; CHECK:   tCMPi8 [[tRSB]], 0, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   [[tRSB:%[0-9]+]]:tgpr, $cpsr = tRSB [[COPY]], 14, $noreg
   ; CHECK:   tBcc %bb.2, 1, $cpsr
   ; CHECK:   tB %bb.1, 14, $noreg
   bb.0:
@@ -163,8 +160,7 @@
   ; CHECK-LABEL: name: test_and
   ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
   ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
-  ; CHECK:   [[tAND:%[0-9]+]]:tgpr, dead $cpsr = tAND [[COPY1]], [[COPY]], 14, $noreg
-  ; CHECK:   tCMPi8 [[tAND]], 0, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   [[tAND:%[0-9]+]]:tgpr, $cpsr = tAND [[COPY1]], [[COPY]], 14, $noreg
   ; CHECK:   tBcc %bb.2, 1, $cpsr
   ; CHECK:   tB %bb.1, 14, $noreg
   bb.0:
@@ -196,8 +192,7 @@
   ; CHECK-LABEL: name: test_orr
   ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
   ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
-  ; CHECK:   [[tORR:%[0-9]+]]:tgpr, dead $cpsr = tORR [[COPY1]], [[COPY]], 14, $noreg
-  ; CHECK:   tCMPi8 [[tORR]], 0, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   [[tORR:%[0-9]+]]:tgpr, $cpsr = tORR [[COPY1]], [[COPY]], 14, $noreg
   ; CHECK:   tBcc %bb.2, 1, $cpsr
   ; CHECK:   tB %bb.1, 14, $noreg
   bb.0:
@@ -229,8 +224,7 @@
   ; CHECK-LABEL: name: test_eor
   ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
   ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
-  ; CHECK:   [[tEOR:%[0-9]+]]:tgpr, dead $cpsr = tEOR [[COPY1]], [[COPY]], 14, $noreg
-  ; CHECK:   tCMPi8 [[tEOR]], 0, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   [[tEOR:%[0-9]+]]:tgpr, $cpsr = tEOR [[COPY1]], [[COPY]], 14, $noreg
   ; CHECK:   tBcc %bb.2, 1, $cpsr
   ; CHECK:   tB %bb.1, 14, $noreg
   bb.0:
@@ -262,8 +256,7 @@
   ; CHECK-LABEL: name: test_bic
   ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
   ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
-  ; CHECK:   [[tBIC:%[0-9]+]]:tgpr, dead $cpsr = tBIC [[COPY1]], [[COPY]], 14, $noreg
-  ; CHECK:   tCMPi8 [[tBIC]], 0, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   [[tBIC:%[0-9]+]]:tgpr, $cpsr = tBIC [[COPY1]], [[COPY]], 14, $noreg
   ; CHECK:   tBcc %bb.2, 1, $cpsr
   ; CHECK:   tB %bb.1, 14, $noreg
   bb.0:
@@ -293,8 +286,7 @@
 body:             |
   ; CHECK-LABEL: name: test_mvn
   ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r0
-  ; CHECK:   [[tMVN:%[0-9]+]]:tgpr, dead $cpsr = tMVN [[COPY]], 14, $noreg
-  ; CHECK:   tCMPi8 [[tMVN]], 0, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   [[tMVN:%[0-9]+]]:tgpr, $cpsr = tMVN [[COPY]], 14, $noreg
   ; CHECK:   tBcc %bb.2, 1, $cpsr
   ; CHECK:   tB %bb.1, 14, $noreg
   bb.0:
@@ -325,8 +317,7 @@
   ; CHECK-LABEL: name: test_asrrr
   ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
   ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
-  ; CHECK:   [[tASRrr:%[0-9]+]]:tgpr, dead $cpsr = tASRrr [[COPY1]], [[COPY]], 14, $noreg
-  ; CHECK:   tCMPi8 [[tASRrr]], 0, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   [[tASRrr:%[0-9]+]]:tgpr, $cpsr = tASRrr [[COPY1]], [[COPY]], 14, $noreg
   ; CHECK:   tBcc %bb.2, 1, $cpsr
   ; CHECK:   tB %bb.1, 14, $noreg
   bb.0:
@@ -356,8 +347,7 @@
 body:             |
   ; CHECK-LABEL: name: test_asrri
   ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r0
-  ; CHECK:   [[tASRri:%[0-9]+]]:tgpr, dead $cpsr = tASRri [[COPY]], 1, 14, $noreg
-  ; CHECK:   tCMPi8 [[tASRri]], 0, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   [[tASRri:%[0-9]+]]:tgpr, $cpsr = tASRri [[COPY]], 1, 14, $noreg
   ; CHECK:   tBcc %bb.2, 1, $cpsr
   ; CHECK:   tB %bb.1, 14, $noreg
   bb.0:
@@ -388,8 +378,7 @@
   ; CHECK-LABEL: name: test_ror
   ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
   ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
-  ; CHECK:   [[tROR:%[0-9]+]]:tgpr, dead $cpsr = tROR [[COPY1]], [[COPY]], 14, $noreg
-  ; CHECK:   tCMPi8 [[tROR]], 0, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   [[tROR:%[0-9]+]]:tgpr, $cpsr = tROR [[COPY1]], [[COPY]], 14, $noreg
   ; CHECK:   tBcc %bb.2, 1, $cpsr
   ; CHECK:   tB %bb.1, 14, $noreg
   bb.0:
Index: test/CodeGen/Thumb/umulo-128-legalisation-lowering.ll
===================================================================
--- test/CodeGen/Thumb/umulo-128-legalisation-lowering.ll
+++ test/CodeGen/Thumb/umulo-128-legalisation-lowering.ll
@@ -45,7 +45,7 @@
 ; THUMBV6-NEXT:    mov r2, r7
 ; THUMBV6-NEXT:    mov r3, r5
 ; THUMBV6-NEXT:    bl __aeabi_lmul
-; THUMBV6-NEXT:    str r1, [sp, #28] @ 4-byte Spill
+; THUMBV6-NEXT:    str r1, [sp, #24] @ 4-byte Spill
 ; THUMBV6-NEXT:    adds r6, r0, r6
 ; THUMBV6-NEXT:    str r4, [sp, #68] @ 4-byte Spill
 ; THUMBV6-NEXT:    mov r0, r4
@@ -58,28 +58,28 @@
 ; THUMBV6-NEXT:    str r0, [sp, #16] @ 4-byte Spill
 ; THUMBV6-NEXT:    mov r0, r5
 ; THUMBV6-NEXT:    adcs r0, r5
-; THUMBV6-NEXT:    str r0, [sp, #64] @ 4-byte Spill
-; THUMBV6-NEXT:    ldr r7, [sp, #104]
+; THUMBV6-NEXT:    str r0, [sp, #60] @ 4-byte Spill
+; THUMBV6-NEXT:    ldr r4, [sp, #104]
 ; THUMBV6-NEXT:    ldr r0, [sp, #72] @ 4-byte Reload
 ; THUMBV6-NEXT:    mov r1, r5
-; THUMBV6-NEXT:    mov r2, r7
+; THUMBV6-NEXT:    mov r2, r4
 ; THUMBV6-NEXT:    mov r3, r5
 ; THUMBV6-NEXT:    bl __aeabi_lmul
 ; THUMBV6-NEXT:    mov r6, r0
 ; THUMBV6-NEXT:    str r1, [sp, #52] @ 4-byte Spill
 ; THUMBV6-NEXT:    ldr r0, [sp, #108]
-; THUMBV6-NEXT:    str r0, [sp, #60] @ 4-byte Spill
+; THUMBV6-NEXT:    str r0, [sp, #32] @ 4-byte Spill
 ; THUMBV6-NEXT:    mov r1, r5
-; THUMBV6-NEXT:    ldr r4, [sp, #44] @ 4-byte Reload
-; THUMBV6-NEXT:    mov r2, r4
+; THUMBV6-NEXT:    ldr r7, [sp, #44] @ 4-byte Reload
+; THUMBV6-NEXT:    mov r2, r7
 ; THUMBV6-NEXT:    mov r3, r5
 ; THUMBV6-NEXT:    bl __aeabi_lmul
-; THUMBV6-NEXT:    str r1, [sp, #32] @ 4-byte Spill
+; THUMBV6-NEXT:    str r1, [sp, #28] @ 4-byte Spill
 ; THUMBV6-NEXT:    adds r6, r0, r6
-; THUMBV6-NEXT:    str r7, [sp, #24] @ 4-byte Spill
-; THUMBV6-NEXT:    mov r0, r7
+; THUMBV6-NEXT:    str r4, [sp, #64] @ 4-byte Spill
+; THUMBV6-NEXT:    mov r0, r4
 ; THUMBV6-NEXT:    mov r1, r5
-; THUMBV6-NEXT:    mov r2, r4
+; THUMBV6-NEXT:    mov r2, r7
 ; THUMBV6-NEXT:    mov r3, r5
 ; THUMBV6-NEXT:    bl __aeabi_lmul
 ; THUMBV6-NEXT:    adds r1, r1, r6
@@ -97,7 +97,7 @@
 ; THUMBV6-NEXT:    ldr r0, [sp, #40] @ 4-byte Reload
 ; THUMBV6-NEXT:    adcs r1, r0
 ; THUMBV6-NEXT:    str r1, [r2, #12]
-; THUMBV6-NEXT:    ldr r1, [sp, #28] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r1, [sp, #24] @ 4-byte Reload
 ; THUMBV6-NEXT:    adcs r5, r5
 ; THUMBV6-NEXT:    movs r0, #1
 ; THUMBV6-NEXT:    cmp r1, #0
@@ -118,42 +118,43 @@
 ; THUMBV6-NEXT:    cmp r1, #0
 ; THUMBV6-NEXT:    mov r2, r0
 ; THUMBV6-NEXT:    ldr r3, [sp, #48] @ 4-byte Reload
-; THUMBV6-NEXT:    ldr r6, [sp, #32] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r7, [sp, #28] @ 4-byte Reload
 ; THUMBV6-NEXT:    bne .LBB0_6
 ; THUMBV6-NEXT:  @ %bb.5: @ %start
 ; THUMBV6-NEXT:    ldr r2, [sp, #80] @ 4-byte Reload
 ; THUMBV6-NEXT:  .LBB0_6: @ %start
 ; THUMBV6-NEXT:    cmp r3, #0
-; THUMBV6-NEXT:    mov r7, r0
+; THUMBV6-NEXT:    mov r6, r0
 ; THUMBV6-NEXT:    ldr r1, [sp, #72] @ 4-byte Reload
 ; THUMBV6-NEXT:    bne .LBB0_8
 ; THUMBV6-NEXT:  @ %bb.7: @ %start
-; THUMBV6-NEXT:    mov r7, r3
+; THUMBV6-NEXT:    mov r6, r3
 ; THUMBV6-NEXT:  .LBB0_8: @ %start
-; THUMBV6-NEXT:    cmp r6, #0
+; THUMBV6-NEXT:    str r6, [sp, #56] @ 4-byte Spill
+; THUMBV6-NEXT:    ldr r6, [sp, #32] @ 4-byte Reload
+; THUMBV6-NEXT:    cmp r7, #0
 ; THUMBV6-NEXT:    mov r3, r0
 ; THUMBV6-NEXT:    bne .LBB0_10
 ; THUMBV6-NEXT:  @ %bb.9: @ %start
-; THUMBV6-NEXT:    mov r3, r6
+; THUMBV6-NEXT:    mov r3, r7
 ; THUMBV6-NEXT:  .LBB0_10: @ %start
 ; THUMBV6-NEXT:    cmp r1, #0
-; THUMBV6-NEXT:    mov r6, r1
+; THUMBV6-NEXT:    mov r7, r1
 ; THUMBV6-NEXT:    mov r1, r0
 ; THUMBV6-NEXT:    bne .LBB0_12
 ; THUMBV6-NEXT:  @ %bb.11: @ %start
-; THUMBV6-NEXT:    mov r1, r6
+; THUMBV6-NEXT:    mov r1, r7
 ; THUMBV6-NEXT:  .LBB0_12: @ %start
-; THUMBV6-NEXT:    str r7, [sp, #72] @ 4-byte Spill
 ; THUMBV6-NEXT:    ands r2, r4
-; THUMBV6-NEXT:    ldr r6, [sp, #60] @ 4-byte Reload
+; THUMBV6-NEXT:    mov r7, r6
 ; THUMBV6-NEXT:    cmp r6, #0
 ; THUMBV6-NEXT:    mov r4, r0
 ; THUMBV6-NEXT:    bne .LBB0_14
 ; THUMBV6-NEXT:  @ %bb.13: @ %start
-; THUMBV6-NEXT:    mov r4, r6
+; THUMBV6-NEXT:    mov r4, r7
 ; THUMBV6-NEXT:  .LBB0_14: @ %start
-; THUMBV6-NEXT:    ldr r7, [sp, #40] @ 4-byte Reload
-; THUMBV6-NEXT:    orrs r2, r7
+; THUMBV6-NEXT:    ldr r6, [sp, #40] @ 4-byte Reload
+; THUMBV6-NEXT:    orrs r2, r6
 ; THUMBV6-NEXT:    ands r4, r1
 ; THUMBV6-NEXT:    orrs r4, r3
 ; THUMBV6-NEXT:    ldr r3, [sp, #52] @ 4-byte Reload
@@ -163,26 +164,23 @@
 ; THUMBV6-NEXT:  @ %bb.15: @ %start
 ; THUMBV6-NEXT:    mov r1, r3
 ; THUMBV6-NEXT:  .LBB0_16: @ %start
-; THUMBV6-NEXT:    ldr r3, [sp, #72] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r3, [sp, #56] @ 4-byte Reload
 ; THUMBV6-NEXT:    orrs r2, r3
 ; THUMBV6-NEXT:    orrs r4, r1
 ; THUMBV6-NEXT:    ldr r1, [sp, #68] @ 4-byte Reload
 ; THUMBV6-NEXT:    ldr r3, [sp, #80] @ 4-byte Reload
 ; THUMBV6-NEXT:    orrs r1, r3
-; THUMBV6-NEXT:    cmp r1, #0
 ; THUMBV6-NEXT:    mov r3, r0
 ; THUMBV6-NEXT:    bne .LBB0_18
 ; THUMBV6-NEXT:  @ %bb.17: @ %start
 ; THUMBV6-NEXT:    mov r3, r1
 ; THUMBV6-NEXT:  .LBB0_18: @ %start
-; THUMBV6-NEXT:    ldr r1, [sp, #64] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r1, [sp, #60] @ 4-byte Reload
 ; THUMBV6-NEXT:    orrs r2, r1
 ; THUMBV6-NEXT:    ldr r1, [sp, #44] @ 4-byte Reload
 ; THUMBV6-NEXT:    orrs r4, r1
-; THUMBV6-NEXT:    ldr r1, [sp, #24] @ 4-byte Reload
-; THUMBV6-NEXT:    orrs r1, r6
-; THUMBV6-NEXT:    mov r6, r1
-; THUMBV6-NEXT:    cmp r1, #0
+; THUMBV6-NEXT:    ldr r6, [sp, #64] @ 4-byte Reload
+; THUMBV6-NEXT:    orrs r6, r7
 ; THUMBV6-NEXT:    mov r1, r0
 ; THUMBV6-NEXT:    bne .LBB0_20
 ; THUMBV6-NEXT:  @ %bb.19: @ %start