Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6691,6 +6691,8 @@
           Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
                               DAG.getConstant(c2 - c1, DL, N1.getValueType()));
         } else {
+          if ((c2 < c1) && N0.getValueType().isVector())
+            return SDValue();
           Mask.lshrInPlace(c1 - c2);
           SDLoc DL(N);
           Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
Index: test/CodeGen/Mips/msa/avoid_shift_combine.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/msa/avoid_shift_combine.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips64el-linux-gnu -mcpu=mips64r6 -mattr=+msa,+fp64 < %s | FileCheck %s
+
+define void @avoid_shift_combine(<2 x i64>* %a, <2 x i64>* %b) {
+; CHECK-LABEL: avoid_shift_combine:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ld.d $w0, 0($4)
+; CHECK-NEXT:    srli.d $w0, $w0, 52
+; CHECK-NEXT:    slli.d $w0, $w0, 51
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    st.d $w0, 0($5)
+entry:
+  %0 = load <2 x i64>, <2 x i64>* %a
+  %1 = tail call <2 x i64> @llvm.mips.srli.d(<2 x i64> %0, i32 52)
+  %2 = tail call <2 x i64> @llvm.mips.slli.d(<2 x i64> %1, i32 51)
+  store <2 x i64> %2, <2 x i64>* %b
+  ret void
+}
+
+declare <2 x i64> @llvm.mips.slli.d(<2 x i64>, i32)
+declare <2 x i64> @llvm.mips.srli.d(<2 x i64>, i32)
Index: test/CodeGen/X86/combine-shl.ll
===================================================================
--- test/CodeGen/X86/combine-shl.ll
+++ test/CodeGen/X86/combine-shl.ll
@@ -575,15 +575,14 @@
 define <4 x i32> @combine_vec_shl_le_lshr0(<4 x i32> %x) {
 ; SSE-LABEL: combine_vec_shl_le_lshr0:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    psrld $2, %xmm0
-; SSE-NEXT:    pand {{.*}}(%rip), %xmm0
+; SSE-NEXT:    psrld $5, %xmm0
+; SSE-NEXT:    pslld $3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: combine_vec_shl_le_lshr0:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [1073741816,1073741816,1073741816,1073741816]
-; AVX-NEXT:    vpsrld $2, %xmm0, %xmm0
-; AVX-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpsrld $5, %xmm0, %xmm0
+; AVX-NEXT:    vpslld $3, %xmm0, %xmm0
 ; AVX-NEXT:    retq
   %1 = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
   %2 = shl <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>