Index: lib/Target/Mips/MipsInstructionSelector.cpp
===================================================================
--- lib/Target/Mips/MipsInstructionSelector.cpp
+++ lib/Target/Mips/MipsInstructionSelector.cpp
@@ -160,6 +160,18 @@
              .add(I.getOperand(1));
     break;
   }
+  case G_PHI: {
+    const unsigned DestReg = I.getOperand(0).getReg();
+    const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
+    const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
+
+    if (DestRegBank != Mips::GPRBRegBankID || OpSize != 32)
+      return false;
+
+    const TargetRegisterClass *DefRC = &Mips::GPR32RegClass;
+    I.setDesc(TII.get(TargetOpcode::PHI));
+    return RBI.constrainGenericRegister(DestReg, *DefRC, MRI);
+  }
   case G_STORE:
   case G_LOAD:
   case G_ZEXTLOAD:
Index: lib/Target/Mips/MipsLegalizerInfo.cpp
===================================================================
--- lib/Target/Mips/MipsLegalizerInfo.cpp
+++ lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -56,6 +56,10 @@
       .legalFor({s32})
       .minScalar(0, s32);
 
+  getActionDefinitionsBuilder(G_PHI)
+      .legalFor({p0, s32})
+      .minScalar(0, s32);
+
   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
       .legalFor({s32})
       .clampScalar(0, s32, s32);
Index: test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
@@ -0,0 +1,71 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define i32 @test_i32(i1 %cnd, i32 %a, i32 %b) {
+  entry:
+    br i1 %cnd, label %cond.true, label %cond.false
+
+  cond.true:                                        ; preds = %entry
+    br label %cond.end
+
+  cond.false:                                       ; preds = %entry
+    br label %cond.end
+
+  cond.end:                                         ; preds = %cond.false, %cond.true
+    %cond = phi i32 [ %a, %cond.true ], [ %b, %cond.false ]
+    ret i32 %cond
+  }
+
+...
+---
+name:            test_i32
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; MIPS32-LABEL: name: test_i32
+  ; MIPS32: bb.0.entry:
+  ; MIPS32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; MIPS32:   liveins: $a0, $a1, $a2
+  ; MIPS32:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+  ; MIPS32:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+  ; MIPS32:   [[LUi:%[0-9]+]]:gpr32 = LUi 0
+  ; MIPS32:   [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+  ; MIPS32:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
+  ; MIPS32:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32:   J %bb.2, implicit-def $at
+  ; MIPS32: bb.1.cond.true:
+  ; MIPS32:   successors: %bb.3(0x80000000)
+  ; MIPS32:   J %bb.3, implicit-def $at
+  ; MIPS32: bb.2.cond.false:
+  ; MIPS32:   successors: %bb.3(0x80000000)
+  ; MIPS32: bb.3.cond.end:
+  ; MIPS32:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
+  ; MIPS32:   $v0 = COPY [[PHI]]
+  ; MIPS32:   RetRA implicit $v0
+  bb.1.entry:
+    liveins: $a0, $a1, $a2
+
+    %3:gprb(s32) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:gprb(s32) = COPY $a2
+    %6:gprb(s32) = G_CONSTANT i32 1
+    %7:gprb(s32) = COPY %3(s32)
+    %5:gprb(s32) = G_AND %7, %6
+    G_BRCOND %5(s32), %bb.2
+    G_BR %bb.3
+
+  bb.2.cond.true:
+    G_BR %bb.4
+
+  bb.3.cond.false:
+
+  bb.4.cond.end:
+    %4:gprb(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
+    $v0 = COPY %4(s32)
+    RetRA implicit $v0
+
+...
Index: test/CodeGen/Mips/GlobalISel/legalizer/phi.mir
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/GlobalISel/legalizer/phi.mir
@@ -0,0 +1,271 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define i1 @test_i1(i1 %cnd, i1 %a, i1 %b) {
+  entry:
+    br i1 %cnd, label %cond.true, label %cond.false
+
+  cond.true:                                        ; preds = %entry
+    br label %cond.end
+
+  cond.false:                                       ; preds = %entry
+    br label %cond.end
+
+  cond.end:                                         ; preds = %cond.false, %cond.true
+    %cond = phi i1 [ %a, %cond.true ], [ %b, %cond.false ]
+    ret i1 %cond
+  }
+
+  define i8 @test_i8(i1 %cnd, i8 %a, i8 %b) {
+  entry:
+    br i1 %cnd, label %cond.true, label %cond.false
+
+  cond.true:                                        ; preds = %entry
+    br label %cond.end
+
+  cond.false:                                       ; preds = %entry
+    br label %cond.end
+
+  cond.end:                                         ; preds = %cond.false, %cond.true
+    %cond = phi i8 [ %a, %cond.true ], [ %b, %cond.false ]
+    ret i8 %cond
+  }
+
+  define i16 @test_i16(i1 %cnd, i16 %a, i16 %b) {
+  entry:
+    br i1 %cnd, label %cond.true, label %cond.false
+
+  cond.true:                                        ; preds = %entry
+    br label %cond.end
+
+  cond.false:                                       ; preds = %entry
+    br label %cond.end
+
+  cond.end:                                         ; preds = %cond.false, %cond.true
+    %cond = phi i16 [ %a, %cond.true ], [ %b, %cond.false ]
+    ret i16 %cond
+  }
+
+  define i32 @test_i32(i1 %cnd, i32 %a, i32 %b) {
+  entry:
+    br i1 %cnd, label %cond.true, label %cond.false
+
+  cond.true:                                        ; preds = %entry
+    br label %cond.end
+
+  cond.false:                                       ; preds = %entry
+    br label %cond.end
+
+  cond.end:                                         ; preds = %cond.false, %cond.true
+    %cond = phi i32 [ %a, %cond.true ], [ %b, %cond.false ]
+    ret i32 %cond
+  }
+
+...
+---
+name:            test_i1
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  ; MIPS32-LABEL: name: test_i1
+  ; MIPS32: bb.0.entry:
+  ; MIPS32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; MIPS32:   liveins: $a0, $a1, $a2
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+  ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; MIPS32:   [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+  ; MIPS32:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+  ; MIPS32:   G_BRCOND [[AND]](s32), %bb.1
+  ; MIPS32:   G_BR %bb.2
+  ; MIPS32: bb.1.cond.true:
+  ; MIPS32:   successors: %bb.3(0x80000000)
+  ; MIPS32:   [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+  ; MIPS32:   G_BR %bb.3
+  ; MIPS32: bb.2.cond.false:
+  ; MIPS32:   successors: %bb.3(0x80000000)
+  ; MIPS32:   [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+  ; MIPS32: bb.3.cond.end:
+  ; MIPS32:   [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY4]](s32), %bb.1, [[COPY5]](s32), %bb.2
+  ; MIPS32:   [[COPY6:%[0-9]+]]:_(s32) = COPY [[PHI]](s32)
+  ; MIPS32:   $v0 = COPY [[COPY6]](s32)
+  ; MIPS32:   RetRA implicit $v0
+  bb.1.entry:
+    liveins: $a0, $a1, $a2
+
+    %3:_(s32) = COPY $a0
+    %0:_(s1) = G_TRUNC %3(s32)
+    %4:_(s32) = COPY $a1
+    %1:_(s1) = G_TRUNC %4(s32)
+    %5:_(s32) = COPY $a2
+    %2:_(s1) = G_TRUNC %5(s32)
+    G_BRCOND %0(s1), %bb.2
+    G_BR %bb.3
+
+  bb.2.cond.true:
+    G_BR %bb.4
+
+  bb.3.cond.false:
+
+  bb.4.cond.end:
+    %6:_(s1) = G_PHI %1(s1), %bb.2, %2(s1), %bb.3
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            test_i8
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  ; MIPS32-LABEL: name: test_i8
+  ; MIPS32: bb.0.entry:
+  ; MIPS32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; MIPS32:   liveins: $a0, $a1, $a2
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+  ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; MIPS32:   [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+  ; MIPS32:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+  ; MIPS32:   G_BRCOND [[AND]](s32), %bb.1
+  ; MIPS32:   G_BR %bb.2
+  ; MIPS32: bb.1.cond.true:
+  ; MIPS32:   successors: %bb.3(0x80000000)
+  ; MIPS32:   [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+  ; MIPS32:   G_BR %bb.3
+  ; MIPS32: bb.2.cond.false:
+  ; MIPS32:   successors: %bb.3(0x80000000)
+  ; MIPS32:   [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+  ; MIPS32: bb.3.cond.end:
+  ; MIPS32:   [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY4]](s32), %bb.1, [[COPY5]](s32), %bb.2
+  ; MIPS32:   [[COPY6:%[0-9]+]]:_(s32) = COPY [[PHI]](s32)
+  ; MIPS32:   $v0 = COPY [[COPY6]](s32)
+  ; MIPS32:   RetRA implicit $v0
+  bb.1.entry:
+    liveins: $a0, $a1, $a2
+
+    %3:_(s32) = COPY $a0
+    %0:_(s1) = G_TRUNC %3(s32)
+    %4:_(s32) = COPY $a1
+    %1:_(s8) = G_TRUNC %4(s32)
+    %5:_(s32) = COPY $a2
+    %2:_(s8) = G_TRUNC %5(s32)
+    G_BRCOND %0(s1), %bb.2
+    G_BR %bb.3
+
+  bb.2.cond.true:
+    G_BR %bb.4
+
+  bb.3.cond.false:
+
+  bb.4.cond.end:
+    %6:_(s8) = G_PHI %1(s8), %bb.2, %2(s8), %bb.3
+    %7:_(s32) = G_ANYEXT %6(s8)
+    $v0 = COPY %7(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            test_i16
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  ; MIPS32-LABEL: name: test_i16
+  ; MIPS32: bb.0.entry:
+  ; MIPS32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; MIPS32:   liveins: $a0, $a1, $a2
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+  ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; MIPS32:   [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+  ; MIPS32:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+  ; MIPS32:   G_BRCOND [[AND]](s32), %bb.1
+  ; MIPS32:   G_BR %bb.2
+  ; MIPS32: bb.1.cond.true:
+  ; MIPS32:   successors: %bb.3(0x80000000)
+  ; MIPS32:   [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+  ; MIPS32:   G_BR %bb.3
+  ; MIPS32: bb.2.cond.false:
+  ; MIPS32:   successors: %bb.3(0x80000000)
+  ; MIPS32:   [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+  ; MIPS32: bb.3.cond.end:
+  ; MIPS32:   [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY4]](s32), %bb.1, [[COPY5]](s32), %bb.2
+  ; MIPS32:   [[COPY6:%[0-9]+]]:_(s32) = COPY [[PHI]](s32)
+  ; MIPS32:   $v0 = COPY [[COPY6]](s32)
+  ; MIPS32:   RetRA implicit $v0
+  bb.1.entry:
+    liveins: $a0, $a1, $a2
+
+    %3:_(s32) = COPY $a0
+    %0:_(s1) = G_TRUNC %3(s32)
+    %4:_(s32) = COPY $a1
+    %1:_(s16) = G_TRUNC %4(s32)
+    %5:_(s32) = COPY $a2
+    %2:_(s16) = G_TRUNC %5(s32)
+    G_BRCOND %0(s1), %bb.2
+    G_BR %bb.3
+
+  bb.2.cond.true:
+    G_BR %bb.4
+
+  bb.3.cond.false:
+
+  bb.4.cond.end:
+    %6:_(s16) = G_PHI %1(s16), %bb.2, %2(s16), %bb.3
+    %7:_(s32) = G_ANYEXT %6(s16)
+    $v0 = COPY %7(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            test_i32
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  ; MIPS32-LABEL: name: test_i32
+  ; MIPS32: bb.0.entry:
+  ; MIPS32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; MIPS32:   liveins: $a0, $a1, $a2
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+  ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; MIPS32:   [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+  ; MIPS32:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+  ; MIPS32:   G_BRCOND [[AND]](s32), %bb.1
+  ; MIPS32:   G_BR %bb.2
+  ; MIPS32: bb.1.cond.true:
+  ; MIPS32:   successors: %bb.3(0x80000000)
+  ; MIPS32:   G_BR %bb.3
+  ; MIPS32: bb.2.cond.false:
+  ; MIPS32:   successors: %bb.3(0x80000000)
+  ; MIPS32: bb.3.cond.end:
+  ; MIPS32:   [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
+  ; MIPS32:   $v0 = COPY [[PHI]](s32)
+  ; MIPS32:   RetRA implicit $v0
+  bb.1.entry:
+    liveins: $a0, $a1, $a2
+
+    %3:_(s32) = COPY $a0
+    %0:_(s1) = G_TRUNC %3(s32)
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = COPY $a2
+    G_BRCOND %0(s1), %bb.2
+    G_BR %bb.3
+
+  bb.2.cond.true:
+    G_BR %bb.4
+
+  bb.3.cond.false:
+
+  bb.4.cond.end:
+    %4:_(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
+    $v0 = COPY %4(s32)
+    RetRA implicit $v0
+
+...
Index: test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll
@@ -0,0 +1,174 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+
+define i1 @test_i1(i1 %cnd, i1 %a, i1 %b) {
+; MIPS32-LABEL: test_i1:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -16
+; MIPS32-NEXT:    .cfi_def_cfa_offset 16
+; MIPS32-NEXT:    lui $1, 0
+; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    sw $5, 12($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    sw $6, 8($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    bnez $1, $BB0_2
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  # %bb.1: # %entry
+; MIPS32-NEXT:    j $BB0_3
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  $BB0_2: # %cond.true
+; MIPS32-NEXT:    lw $1, 12($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    sw $1, 4($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    j $BB0_4
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  $BB0_3: # %cond.false
+; MIPS32-NEXT:    lw $1, 8($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    sw $1, 4($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:  $BB0_4: # %cond.end
+; MIPS32-NEXT:    lw $1, 4($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    addiu $sp, $sp, 16
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  br i1 %cnd, label %cond.true, label %cond.false
+
+cond.true:
+  br label %cond.end
+
+cond.false:
+  br label %cond.end
+
+cond.end:
+  %cond = phi i1 [ %a, %cond.true ], [ %b, %cond.false ]
+  ret i1 %cond
+}
+
+define i8 @test_i8(i1 %cnd, i8 %a, i8 %b) {
+; MIPS32-LABEL: test_i8:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -16
+; MIPS32-NEXT:    .cfi_def_cfa_offset 16
+; MIPS32-NEXT:    lui $1, 0
+; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    sw $5, 12($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    sw $6, 8($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    bnez $1, $BB1_2
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  # %bb.1: # %entry
+; MIPS32-NEXT:    j $BB1_3
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  $BB1_2: # %cond.true
+; MIPS32-NEXT:    lw $1, 12($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    sw $1, 4($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    j $BB1_4
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  $BB1_3: # %cond.false
+; MIPS32-NEXT:    lw $1, 8($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    sw $1, 4($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:  $BB1_4: # %cond.end
+; MIPS32-NEXT:    lw $1, 4($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    addiu $sp, $sp, 16
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  br i1 %cnd, label %cond.true, label %cond.false
+
+cond.true:
+  br label %cond.end
+
+cond.false:
+  br label %cond.end
+
+cond.end:
+  %cond = phi i8 [ %a, %cond.true ], [ %b, %cond.false ]
+  ret i8 %cond
+}
+
+define i16 @test_i16(i1 %cnd, i16 %a, i16 %b) {
+; MIPS32-LABEL: test_i16:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -16
+; MIPS32-NEXT:    .cfi_def_cfa_offset 16
+; MIPS32-NEXT:    lui $1, 0
+; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    sw $5, 12($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    sw $6, 8($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    bnez $1, $BB2_2
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  # %bb.1: # %entry
+; MIPS32-NEXT:    j $BB2_3
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  $BB2_2: # %cond.true
+; MIPS32-NEXT:    lw $1, 12($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    sw $1, 4($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    j $BB2_4
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  $BB2_3: # %cond.false
+; MIPS32-NEXT:    lw $1, 8($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    sw $1, 4($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:  $BB2_4: # %cond.end
+; MIPS32-NEXT:    lw $1, 4($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    addiu $sp, $sp, 16
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  br i1 %cnd, label %cond.true, label %cond.false
+
+cond.true:
+  br label %cond.end
+
+cond.false:
+  br label %cond.end
+
+cond.end:
+  %cond = phi i16 [ %a, %cond.true ], [ %b, %cond.false ]
+  ret i16 %cond
+}
+
+define i32 @test_i32(i1 %cnd, i32 %a, i32 %b) {
+; MIPS32-LABEL: test_i32:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -16
+; MIPS32-NEXT:    .cfi_def_cfa_offset 16
+; MIPS32-NEXT:    lui $1, 0
+; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    sw $5, 12($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    sw $6, 8($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    bnez $1, $BB3_2
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  # %bb.1: # %entry
+; MIPS32-NEXT:    j $BB3_3
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  $BB3_2: # %cond.true
+; MIPS32-NEXT:    lw $1, 12($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    sw $1, 4($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    j $BB3_4
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  $BB3_3: # %cond.false
+; MIPS32-NEXT:    lw $1, 8($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    sw $1, 4($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:  $BB3_4: # %cond.end
+; MIPS32-NEXT:    lw $1, 4($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    addiu $sp, $sp, 16
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  br i1 %cnd, label %cond.true, label %cond.false
+
+cond.true:
+  br label %cond.end
+
+cond.false:
+  br label %cond.end
+
+cond.end:
+  %cond = phi i32 [ %a, %cond.true ], [ %b, %cond.false ]
+  ret i32 %cond
+}
Index: test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir
@@ -0,0 +1,70 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define i32 @test_i32(i1 %cnd, i32 %a, i32 %b) {
+  entry:
+    br i1 %cnd, label %cond.true, label %cond.false
+
+  cond.true:                                        ; preds = %entry
+    br label %cond.end
+
+  cond.false:                                       ; preds = %entry
+    br label %cond.end
+
+  cond.end:                                         ; preds = %cond.false, %cond.true
+    %cond = phi i32 [ %a, %cond.true ], [ %b, %cond.false ]
+    ret i32 %cond
+  }
+
+...
+---
+name:            test_i32
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  ; MIPS32-LABEL: name: test_i32
+  ; MIPS32: bb.0.entry:
+  ; MIPS32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; MIPS32:   liveins: $a0, $a1, $a2
+  ; MIPS32:   [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+  ; MIPS32:   [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
+  ; MIPS32:   [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+  ; MIPS32:   [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
+  ; MIPS32:   [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
+  ; MIPS32:   G_BRCOND [[AND]](s32), %bb.1
+  ; MIPS32:   G_BR %bb.2
+  ; MIPS32: bb.1.cond.true:
+  ; MIPS32:   successors: %bb.3(0x80000000)
+  ; MIPS32:   G_BR %bb.3
+  ; MIPS32: bb.2.cond.false:
+  ; MIPS32:   successors: %bb.3(0x80000000)
+  ; MIPS32: bb.3.cond.end:
+  ; MIPS32:   [[PHI:%[0-9]+]]:gprb(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
+  ; MIPS32:   $v0 = COPY [[PHI]](s32)
+  ; MIPS32:   RetRA implicit $v0
+  bb.1.entry:
+    liveins: $a0, $a1, $a2
+
+    %3:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = COPY $a2
+    %6:_(s32) = G_CONSTANT i32 1
+    %7:_(s32) = COPY %3(s32)
+    %5:_(s32) = G_AND %7, %6
+    G_BRCOND %5(s32), %bb.2
+    G_BR %bb.3
+
+  bb.2.cond.true:
+    G_BR %bb.4
+
+  bb.3.cond.false:
+
+  bb.4.cond.end:
+    %4:_(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
+    $v0 = COPY %4(s32)
+    RetRA implicit $v0
+
+...