Index: lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1278,6 +1278,16 @@
     Known.Zero = Known2.Zero.reverseBits();
     break;
   }
+  case ISD::BSWAP: {
+    SDValue Src = Op.getOperand(0);
+    APInt DemandedSrcBits = DemandedBits.byteSwap();
+    if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO,
+                             Depth + 1))
+      return true;
+    Known.One = Known2.One.byteSwap();
+    Known.Zero = Known2.Zero.byteSwap();
+    break;
+  }
   case ISD::SIGN_EXTEND_INREG: {
     SDValue Op0 = Op.getOperand(0);
     EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
Index: test/CodeGen/AArch64/arm64-rev.ll
===================================================================
--- test/CodeGen/AArch64/arm64-rev.ll
+++ test/CodeGen/AArch64/arm64-rev.ll
@@ -37,8 +37,8 @@
 define i32 @test_rev_w_srl16(i16 %a) {
 ; CHECK-LABEL: test_rev_w_srl16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    and w8, w0, #0xffff
-; CHECK-NEXT:    rev16 w0, w8
+; CHECK-NEXT:    rev w8, w0
+; CHECK-NEXT:    lsr w0, w8, #16
 ; CHECK-NEXT:    ret
 entry:
   %0 = zext i16 %a to i32
@@ -51,7 +51,8 @@
 ; CHECK-LABEL: test_rev_w_srl16_load:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ldrh w8, [x0]
-; CHECK-NEXT:    rev16 w0, w8
+; CHECK-NEXT:    rev w8, w8
+; CHECK-NEXT:    lsr w0, w8, #16
 ; CHECK-NEXT:    ret
 entry:
   %0 = load i16, i16 *%a
@@ -82,8 +83,9 @@
 define i64 @test_rev_x_srl32(i32 %a) {
 ; CHECK-LABEL: test_rev_x_srl32:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, w0
-; CHECK-NEXT:    rev32 x0, x8
+; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT:    rev x8, x0
+; CHECK-NEXT:    lsr x0, x8, #32
 ; CHECK-NEXT:    ret
 entry:
   %0 = zext i32 %a to i64
@@ -96,7 +98,8 @@
 ; CHECK-LABEL: test_rev_x_srl32_load:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    rev32 x0, x8
+; CHECK-NEXT:    rev x8, x8
+; CHECK-NEXT:    lsr x0, x8, #32
 ; CHECK-NEXT:    ret
 entry:
   %0 = load i32, i32 *%a
Index: test/CodeGen/AMDGPU/bswap.ll
===================================================================
--- test/CodeGen/AMDGPU/bswap.ll
+++ test/CodeGen/AMDGPU/bswap.ll
@@ -732,7 +732,6 @@
 ; VI-LABEL: missing_truncate_promote_bswap:
 ; VI:       ; %bb.0: ; %bb
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
 ; VI-NEXT:    v_alignbit_b32 v1, v0, v0, 8
 ; VI-NEXT:    v_alignbit_b32 v0, v0, v0, 24
 ; VI-NEXT:    s_mov_b32 s6, 0xff00ff
Index: test/CodeGen/PowerPC/pr39478.ll
===================================================================
--- test/CodeGen/PowerPC/pr39478.ll
+++ test/CodeGen/PowerPC/pr39478.ll
@@ -5,13 +5,17 @@
 define void @pr39478(i64* %p64, i32* %p32) {
 ; CHECKLE-LABEL: pr39478:
 ; CHECKLE:       # %bb.0: # %entry
-; CHECKLE-NEXT:    lbz 3, 4(3)
+; CHECKLE-NEXT:    ld 3, 0(3)
+; CHECKLE-NEXT:    rldicl 3, 3, 56, 8
+; CHECKLE-NEXT:    srwi 3, 3, 24
 ; CHECKLE-NEXT:    stb 3, 0(4)
 ; CHECKLE-NEXT:    blr
 ;
 ; CHECKBE-LABEL: pr39478:
 ; CHECKBE:       # %bb.0: # %entry
-; CHECKBE-NEXT:    lbz 3, 3(3)
+; CHECKBE-NEXT:    ld 3, 0(3)
+; CHECKBE-NEXT:    rldicl 3, 3, 56, 8
+; CHECKBE-NEXT:    srwi 3, 3, 24
 ; CHECKBE-NEXT:    stb 3, 3(4)
 ; CHECKBE-NEXT:    blr
 entry:
Index: test/CodeGen/X86/combine-bswap.ll
===================================================================
--- test/CodeGen/X86/combine-bswap.ll
+++ test/CodeGen/X86/combine-bswap.ll
@@ -40,8 +40,7 @@
 define i32 @test_demandedbits_bswap(i32 %a0) nounwind {
 ; X86-LABEL: test_demandedbits_bswap:
 ; X86:       # %bb.0:
-; X86-NEXT:    movl $-16777216, %eax # imm = 0xFF000000
-; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    bswapl %eax
 ; X86-NEXT:    andl $-65536, %eax # imm = 0xFFFF0000
 ; X86-NEXT:    retl
@@ -49,7 +48,6 @@
 ; X64-LABEL: test_demandedbits_bswap:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    orl $-16777216, %eax # imm = 0xFF000000
 ; X64-NEXT:    bswapl %eax
 ; X64-NEXT:    andl $-65536, %eax # imm = 0xFFFF0000
 ; X64-NEXT:    retq