Index: lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1064,6 +1064,26 @@
     }
     break;
   }
+  case ISD::BITREVERSE: {
+    SDValue Src = Op.getOperand(0);
+    APInt DemandedSrcBits = DemandedBits.reverseBits();
+    if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO,
+                             Depth + 1))
+      return true;
+    Known.One = Known2.One.reverseBits();
+    Known.Zero = Known2.Zero.reverseBits();
+    break;
+  }
+  case ISD::BSWAP: {
+    SDValue Src = Op.getOperand(0);
+    APInt DemandedSrcBits = DemandedBits.byteSwap();
+    if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO,
+                             Depth + 1))
+      return true;
+    Known.One = Known2.One.byteSwap();
+    Known.Zero = Known2.Zero.byteSwap();
+    break;
+  }
   case ISD::SIGN_EXTEND_INREG: {
     SDValue Op0 = Op.getOperand(0);
     EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
Index: test/CodeGen/AArch64/arm64-rev.ll
===================================================================
--- test/CodeGen/AArch64/arm64-rev.ll
+++ test/CodeGen/AArch64/arm64-rev.ll
@@ -26,8 +26,8 @@
 define i32 @test_rev_w_srl16(i16 %a) {
 ; CHECK-LABEL: test_rev_w_srl16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    and w8, w0, #0xffff
-; CHECK-NEXT:    rev16 w0, w8
+; CHECK-NEXT:    rev w8, w0
+; CHECK-NEXT:    lsr w0, w8, #16
 ; CHECK-NEXT:    ret
 entry:
   %0 = zext i16 %a to i32
@@ -41,8 +41,9 @@
 define i64 @test_rev_x_srl32(i32 %a) {
 ; CHECK-LABEL: test_rev_x_srl32:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, w0
-; CHECK-NEXT:    rev32 x0, x8
+; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT:    rev x8, x0
+; CHECK-NEXT:    lsr x0, x8, #32
 ; CHECK-NEXT:    ret
 entry:
   %0 = zext i32 %a to i64
Index: test/CodeGen/AMDGPU/bitreverse.ll
===================================================================
--- test/CodeGen/AMDGPU/bitreverse.ll
+++ test/CodeGen/AMDGPU/bitreverse.ll
@@ -114,7 +114,8 @@
 }
 
 ; FUNC-LABEL: {{^}}missing_truncate_promote_bitreverse:
-; VI: v_bfrev_b32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; VI: v_bfrev_b32_e32 v0, v0
+; VI: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
 define float @missing_truncate_promote_bitreverse(i32 %arg) {
 bb:
   %tmp = trunc i32 %arg to i16
Index: test/CodeGen/AMDGPU/bswap.ll
===================================================================
--- test/CodeGen/AMDGPU/bswap.ll
+++ test/CodeGen/AMDGPU/bswap.ll
@@ -118,7 +118,7 @@
 }
 
 ; GCN-LABEL: {{^}}missing_truncate_promote_bswap:
-; VI: v_and_b32
+; VI-NOT: v_and_b32
 ; VI: v_alignbit_b32
 ; VI: v_alignbit_b32
 ; VI: v_bfi_b32
Index: test/CodeGen/PowerPC/pr39478.ll
===================================================================
--- test/CodeGen/PowerPC/pr39478.ll
+++ test/CodeGen/PowerPC/pr39478.ll
@@ -7,7 +7,9 @@
 define void @pr39478() {
 ; CHECK-LABEL: pr39478:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    ld 3, 0(3)
+; CHECK-NEXT:    rldicl 3, 3, 56, 8
+; CHECK-NEXT:    srwi 3, 3, 24
 ; CHECK-NEXT:    stb 3, 0(3)
 ; CHECK-NEXT:    blr
 entry:
Index: test/CodeGen/X86/combine-bitreverse.ll
===================================================================
--- test/CodeGen/X86/combine-bitreverse.ll
+++ test/CodeGen/X86/combine-bitreverse.ll
@@ -40,7 +40,6 @@
 define <4 x i32> @test_demandedbits_bitreverse(<4 x i32> %a0) nounwind {
 ; X86-LABEL: test_demandedbits_bitreverse:
 ; X86:       # %bb.0:
-; X86-NEXT:    por {{\.LCPI.*}}, %xmm0
 ; X86-NEXT:    pxor %xmm1, %xmm1
 ; X86-NEXT:    movdqa %xmm0, %xmm2
 ; X86-NEXT:    punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
@@ -79,7 +78,6 @@
 ;
 ; X64-LABEL: test_demandedbits_bitreverse:
 ; X64:       # %bb.0:
-; X64-NEXT:    vpor {{.*}}(%rip), %xmm0, %xmm0
 ; X64-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
 ; X64-NEXT:    vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
 ; X64-NEXT:    vpand %xmm1, %xmm0, %xmm2
Index: test/CodeGen/X86/combine-bswap.ll
===================================================================
--- test/CodeGen/X86/combine-bswap.ll
+++ test/CodeGen/X86/combine-bswap.ll
@@ -40,8 +40,7 @@
 define i32 @test_demandedbits_bswap(i32 %a0) nounwind {
 ; X86-LABEL: test_demandedbits_bswap:
 ; X86:       # %bb.0:
-; X86-NEXT:    movl $-16777216, %eax # imm = 0xFF000000
-; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    bswapl %eax
 ; X86-NEXT:    andl $-65536, %eax # imm = 0xFFFF0000
 ; X86-NEXT:    retl
@@ -49,7 +48,6 @@
 ; X64-LABEL: test_demandedbits_bswap:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    orl $-16777216, %eax # imm = 0xFF000000
 ; X64-NEXT:    bswapl %eax
 ; X64-NEXT:    andl $-65536, %eax # imm = 0xFFFF0000
 ; X64-NEXT:    retq