Index: lib/Target/Mips/MipsSEFrameLowering.cpp
===================================================================
--- lib/Target/Mips/MipsSEFrameLowering.cpp
+++ lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -372,6 +372,12 @@
     unsigned SrcReg = I->getOperand(1).getReg();
     unsigned N = I->getOperand(2).getImm();
     int64_t Offset = 4 * (Subtarget.isLittle() ? N : (1 - N));
+    // We should store the source register to the stack only when we are
+    // extracting the first element of the pair (which is endianness-dependent)
+    // For the other element of pair the source register will be already saved
+    // on the stack.
+    bool ShouldStoreSrcReg = (Subtarget.isLittle()  && N == 0) ||
+                             (!Subtarget.isLittle() && N == 1);
 
     // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
     // the cases where mfhc1 is not available). 64-bit architectures and
@@ -386,8 +392,11 @@
     // We re-use the same spill slot each time so that the stack frame doesn't
     // grow too much in functions with a large number of moves.
     int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC);
-    TII.storeRegToStack(MBB, I, SrcReg, I->getOperand(1).isKill(), FI, RC, &TRI,
-                        0);
+
+    if (ShouldStoreSrcReg) {
+      TII.storeRegToStack(MBB, I, SrcReg, I->getOperand(1).isKill(),
+                          FI, RC, &TRI, 0);
+    }
     TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, Offset);
     return true;
   }
Index: test/CodeGen/Mips/fp64a.ll
===================================================================
--- test/CodeGen/Mips/fp64a.ll
+++ test/CodeGen/Mips/fp64a.ll
@@ -153,8 +153,6 @@
 ; 32R2-FP64A:           addiu   $sp, $sp, -32
 ; 32R2-FP64A:           sdc1    $f0, 16($sp)
 ; 32R2-FP64A:           lw      $6, 16($sp)
-; FIXME: This store is redundant
-; 32R2-FP64A:           sdc1    $f0, 16($sp)
 ; 32R2-FP64A:           lw      $7, 20($sp)
 
 ; 64-NO-FP64A:          mov.d   $f13, $f0
Index: test/CodeGen/Mips/fpxx.ll
===================================================================
--- test/CodeGen/Mips/fpxx.ll
+++ test/CodeGen/Mips/fpxx.ll
@@ -195,8 +195,6 @@
 ; 32-FPXX:         addiu   $sp, $sp, -32
 ; 32-FPXX:         sdc1    $f0, 16($sp)
 ; 32-FPXX:         lw      $6, 16($sp)
-; FIXME: This store is redundant
-; 32-FPXX:         sdc1    $f0, 16($sp)
 ; 32-FPXX:         lw      $7, 20($sp)
 
 ; 32R2-NOFPXX-DAG: mfc1    $6, $f0