Index: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td =================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td @@ -2147,6 +2147,11 @@ def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm), (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>; +// Do the same for v8m targets since they support movw with a 16-bit value. +def : T1Pat<(add tGPR:$src, imm0_65535_neg:$imm), + (tSUBrr tGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>, + Requires<[HasV8MBaseline]>; + let AddedComplexity = 1 in def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm), (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>; Index: llvm/trunk/test/CodeGen/ARM/sub.ll =================================================================== --- llvm/trunk/test/CodeGen/ARM/sub.ll +++ llvm/trunk/test/CodeGen/ARM/sub.ll @@ -1,10 +1,13 @@ -; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -show-mc-encoding -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE ; RUN: llc -mtriple=armeb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE +; RUN: llc -mtriple=thumbv6m %s -o - | FileCheck %s --check-prefix=CHECK-V6M +; RUN: llc -mtriple=thumbv8m.base -show-mc-encoding %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8M +; RUN: llc -mtriple=thumbv8m.main -show-mc-encoding %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8M ; 171 = 0x000000ab define i64 @f1(i64 %a) { -; CHECK: f1 -; CHECK-LE: subs r0, r0, #171 +; CHECK-LABEL: f1 +; CHECK-LE: subs{{.*}} r0, #171 ; CHECK-LE: sbc r1, r1, #0 ; CHECK-BE: subs r1, r1, #171 ; CHECK-BE: sbc r0, r0, #0 @@ -14,8 +17,8 @@ ; 66846720 = 0x03fc0000 define i64 @f2(i64 %a) { -; CHECK: f2 -; CHECK-LE: subs r0, r0, #66846720 +; CHECK-LABEL: f2 +; CHECK-LE: subs{{.*}} r0, r0, #66846720 ; CHECK-LE: sbc r1, r1, #0 ; CHECK-BE: subs r1, r1, #66846720 ; CHECK-BE: sbc r0, r0, #0 @@ -25,8 +28,8 @@ ; 734439407618 = 0x000000ab00000002 define i64 @f3(i64 %a) { -; CHECK: f3 -; CHECK-LE: subs r0, r0, #2 +; CHECK-LABEL: f3 +; CHECK-LE: subs{{.*}} r0, #2 ; CHECK-LE: sbc r1, r1, #171 ; CHECK-BE: subs r1, r1, #2 ; CHECK-BE: sbc r0, r0, #171 @@ -36,22 +39,47 @@ define i32 @f4(i32 %x) { entry: -; CHECK: f4 -; CHECK: rsbs +; CHECK-LABEL: f4 +; CHECK-LE: rsbs +; CHECK-BE: rsbs %sub = sub i32 1, %x %cmp = icmp ugt i32 %sub, 0 %sel = select i1 %cmp, i32 1, i32 %sub ret i32 %sel } -; rdar://11726136 define i32 @f5(i32 %x) { entry: -; CHECK: f5 -; CHECK: movw r1, #65535 +; CHECK-LABEL: f5: +; CHECK-LE: movw r1, #65535 @ encoding: [0xff,0x1f,0x0f,0xe3] +; CHECK-V8M: movw r1, #65535 @ encoding: [0x4f,0xf6,0xff,0x71] ; CHECK-NOT: movt ; CHECK-NOT: add -; CHECK: sub r0, r0, r1 +; CHECK: sub{{.*}} r0, r0, r1 + +; CHECK-V6M-LABEL: f5 +; CHECK-V6M: ldr [[NEG:r[0-1]+]], [[CONST:.[A-Z0-9_]+]] +; CHECK-V6M: add{{.*}} r0, [[NEG]] +; CHECK-V6M: [[CONST]] +; CHECK-V6M: .long 4294901761 %sub = add i32 %x, -65535 ret i32 %sub } + +define i32 @f6(i32 %x) { +entry: +; CHECK-LABEL: f6: +; CHECK-LE: movw r1, #65535 @ encoding: [0xff,0x1f,0x0f,0xe3] +; CHECK-V8M: movw r1, #65535 @ encoding: [0x4f,0xf6,0xff,0x71] +; CHECK-NOT: movt +; CHECK-NOT: sub +; CHECK: add{{.*}} r0, r1 + +; CHECK-V6M-LABEL: f6 +; CHECK-V6M: ldr [[NEG:r[0-1]+]], [[CONST:.[A-Z0-9_]+]] +; CHECK-V6M: add{{.*}} r0, [[NEG]] +; CHECK-V6M: [[CONST]] +; CHECK-V6M: .long 65535 + %sub = sub i32 %x, -65535 + ret i32 %sub +}