Index: lib/Target/ARM/ARMInstrThumb.td
===================================================================
--- lib/Target/ARM/ARMInstrThumb.td
+++ lib/Target/ARM/ARMInstrThumb.td
@@ -1322,6 +1322,10 @@
 def : tInstAlias <"sub${s}${p} $Rdn, $Rm",
                  (tSUBrr tGPR:$Rdn,s_cc_out:$s, tGPR:$Rdn, tGPR:$Rm, pred:$p)>;
 
+def : T1Pat<(add tGPR:$src, imm0_65535_neg:$imm),
+             (tSUBrr tGPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
+             Requires<[HasV8MBaseline]>;
+
 /// Similar to the above except these set the 's' bit so the
 /// instruction modifies the CPSR register.
 ///
Index: test/CodeGen/ARM/sub.ll
===================================================================
--- test/CodeGen/ARM/sub.ll
+++ test/CodeGen/ARM/sub.ll
@@ -1,10 +1,13 @@
 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
 ; RUN: llc -mtriple=armeb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
+; RUN: llc -mtriple=thumbv6m %s -o - | FileCheck %s --check-prefix=CHECK-V6M
+; RUN: llc -mtriple=thumbv8m.base %s -o - | FileCheck %s --check-prefix=CHECK
+; RUN: llc -mtriple=thumbv8m.main %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
 
 ; 171 = 0x000000ab
 define i64 @f1(i64 %a) {
 ; CHECK: f1
-; CHECK-LE: subs r0, r0, #171
+; CHECK-LE: subs{{.*}} r0, #171
 ; CHECK-LE: sbc r1, r1, #0
 ; CHECK-BE: subs r1, r1, #171
 ; CHECK-BE: sbc r0, r0, #0
@@ -15,7 +18,7 @@
 ; 66846720 = 0x03fc0000
 define i64 @f2(i64 %a) {
 ; CHECK: f2
-; CHECK-LE: subs r0, r0, #66846720
+; CHECK-LE: subs{{.*}} r0, r0, #66846720
 ; CHECK-LE: sbc r1, r1, #0
 ; CHECK-BE: subs r1, r1, #66846720
 ; CHECK-BE: sbc r0, r0, #0
@@ -26,7 +29,7 @@
 ; 734439407618 = 0x000000ab00000002
 define i64 @f3(i64 %a) {
 ; CHECK: f3
-; CHECK-LE: subs r0, r0, #2
+; CHECK-LE: subs{{.*}} r0, #2
 ; CHECK-LE: sbc r1, r1, #171
 ; CHECK-BE: subs r1, r1, #2
 ; CHECK-BE: sbc r0, r0, #171
@@ -37,21 +40,38 @@
 define i32 @f4(i32 %x) {
 entry:
 ; CHECK: f4
-; CHECK: rsbs
+; CHECK-LE: rsbs
+; CHECK-BE: rsbs
   %sub = sub i32 1, %x
   %cmp = icmp ugt i32 %sub, 0
   %sel = select i1 %cmp, i32 1, i32 %sub
   ret i32 %sel
 }
 
-; rdar://11726136
 define i32 @f5(i32 %x) {
 entry:
 ; CHECK: f5
 ; CHECK: movw r1, #65535
 ; CHECK-NOT: movt
 ; CHECK-NOT: add
-; CHECK: sub r0, r0, r1
+; CHECK: sub{{.*}} r0, r0, r1
+
+; CHECK-V6M: f5
+; CHECK-V6M: ldr
   %sub = add i32 %x, -65535
   ret i32 %sub
 }
+
+define i32 @f6(i32 %x) {
+entry:
+; CHECK: f6
+; CHECK: movw r1, #65535
+; CHECK-NOT: movt
+; CHECK-NOT: sub
+; CHECK: add{{.*}} r0, r1
+
+; CHECK-V6M: f6
+; CHECK-V6M: ldr
+  %sub = sub i32 %x, -65535
+  ret i32 %sub
+}