Index: lib/Target/AMDGPU/AMDGPU.td =================================================================== --- lib/Target/AMDGPU/AMDGPU.td +++ lib/Target/AMDGPU/AMDGPU.td @@ -424,31 +424,25 @@ "Dummy feature to disable assembler instructions" >; -def FeatureGCN : SubtargetFeature<"gcn", - "IsGCN", - "true", - "GCN or newer GPU" ->; - class GCNSubtargetFeatureGeneration Implies> : SubtargetFeatureGeneration ; def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS", [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128, - FeatureWavefrontSize64, FeatureGCN, + FeatureWavefrontSize64, FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange] >; def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS", [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128, - FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace, + FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange] >; def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS", [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128, - FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN, + FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts, FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel, FeatureScalarStores, FeatureInv2PiInlineImm, @@ -459,7 +453,7 @@ def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9", [FeatureFP64, FeatureLocalMemorySize65536, - FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN, + FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts, FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm, FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode, Index: lib/Target/AMDGPU/AMDGPUInstructions.td =================================================================== --- lib/Target/AMDGPU/AMDGPUInstructions.td +++ lib/Target/AMDGPU/AMDGPUInstructions.td @@ -65,12 +65,8 @@ def TruePredicate : Predicate<"true">; -// Exists to help track down where SubtargetPredicate isn't set rather -// than letting tablegen crash with an unhelpful error. -def InvalidPred : Predicate<"predicate not set on instruction or pattern">; - class PredicateControl { - Predicate SubtargetPredicate = InvalidPred; + Predicate SubtargetPredicate = TruePredicate; list AssemblerPredicates = []; Predicate AssemblerPredicate = TruePredicate; list OtherPredicates = []; @@ -625,9 +621,7 @@ : AMDGPUPat< (sub_type (extractelt vec_type:$src, sub_idx)), (EXTRACT_SUBREG $src, sub_reg) -> { - let SubtargetPredicate = TruePredicate; -} +>; /* Insert element pattern */ class Insert_Element { - let SubtargetPredicate = TruePredicate; -} +>; // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer // can handle COPY instructions. Index: lib/Target/AMDGPU/AMDGPUSubtarget.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -123,6 +123,10 @@ HasMovrel = true; } + // Don't crash on invalid devices. + if (WavefrontSize == 0) + WavefrontSize = 64; + HasFminFmaxLegacy = getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS; return *this; Index: lib/Target/AMDGPU/DSInstructions.td =================================================================== --- lib/Target/AMDGPU/DSInstructions.td +++ lib/Target/AMDGPU/DSInstructions.td @@ -10,8 +10,6 @@ InstSI , SIMCInstr { - let SubtargetPredicate = isGCN; - let LGKM_CNT = 1; let DS = 1; let Size = 8; Index: lib/Target/AMDGPU/GCNProcessors.td =================================================================== --- lib/Target/AMDGPU/GCNProcessors.td +++ lib/Target/AMDGPU/GCNProcessors.td @@ -9,7 +9,7 @@ // The code produced for "generic" is only useful for tests and cannot // reasonably be expected to execute on any particular target. def : ProcessorModel<"generic", NoSchedModel, - [FeatureGCN, FeatureWavefrontSize64] + [FeatureWavefrontSize64] >; //===----------------------------------------------------------------------===// Index: lib/Target/AMDGPU/MIMGInstructions.td =================================================================== --- lib/Target/AMDGPU/MIMGInstructions.td +++ lib/Target/AMDGPU/MIMGInstructions.td @@ -101,7 +101,6 @@ let UseNamedOperandTable = 1; let hasSideEffects = 0; // XXX ???? - let SubtargetPredicate = isGCN; let DecoderNamespace = dns; let isAsmParserOnly = !if(!eq(dns,""), 1, 0); let AsmMatchConverter = "cvtMIMG"; Index: lib/Target/AMDGPU/SIInstrFormats.td =================================================================== --- lib/Target/AMDGPU/SIInstrFormats.td +++ lib/Target/AMDGPU/SIInstrFormats.td @@ -10,9 +10,6 @@ // //===----------------------------------------------------------------------===// -def isGCN : Predicate<"Subtarget->getGeneration() " - ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">, - AssemblerPredicate<"FeatureGCN">; def isSI : Predicate<"Subtarget->getGeneration() " "== AMDGPUSubtarget::SOUTHERN_ISLANDS">, AssemblerPredicate<"FeatureSouthernIslands">; @@ -21,8 +18,6 @@ class InstSI pattern = []> : AMDGPUInst, GCNPredicateControl { - let SubtargetPredicate = isGCN; - // Low bits - basic encoding information. field bit SALU = 0; field bit VALU = 0; Index: lib/Target/AMDGPU/SIInstructions.td =================================================================== --- lib/Target/AMDGPU/SIInstructions.td +++ lib/Target/AMDGPU/SIInstructions.td @@ -11,7 +11,7 @@ //===----------------------------------------------------------------------===// class GCNPat : Pat, GCNPredicateControl { - let SubtargetPredicate = isGCN; + } include "SOPInstructions.td" @@ -581,7 +581,7 @@ // VOP1 Patterns //===----------------------------------------------------------------------===// -let SubtargetPredicate = isGCN, OtherPredicates = [UnsafeFPMath] in { +let OtherPredicates = [UnsafeFPMath] in { //def : RcpPat; //defm : RsqPat; @@ -604,7 +604,7 @@ (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE) >; -} // End SubtargetPredicate = isGCN, OtherPredicates = [UnsafeFPMath] +} // End OtherPredicates = [UnsafeFPMath] // f16_to_fp patterns @@ -807,8 +807,6 @@ (v2f16 (EXTRACT_SUBREG v4f16:$vec, sub1)) >; -let SubtargetPredicate = isGCN in { - // FIXME: Why do only some of these type combinations for SReg and // VReg? // 16-bit bitcast @@ -891,8 +889,6 @@ def : BitConvert ; def : BitConvert ; -} // End SubtargetPredicate = isGCN - /********** =================== **********/ /********** Src & Dst modifiers **********/ /********** =================== **********/ @@ -1104,9 +1100,7 @@ /********** Intrinsic Patterns **********/ /********** ================== **********/ -let SubtargetPredicate = isGCN in { def : POW_Common ; -} def : GCNPat < (i32 (sext i1:$src0)), @@ -1133,8 +1127,6 @@ // VOP3 Patterns //===----------------------------------------------------------------------===// -let SubtargetPredicate = isGCN in { - def : IMad24Pat; def : UMad24Pat; @@ -1142,8 +1134,6 @@ defm : BFIPatterns ; def : ROTRPattern ; -} - def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))), (V_ALIGNBIT_B32 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)), (i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>; @@ -1611,8 +1601,6 @@ >; } -let SubtargetPredicate = isGCN in { - defm : BFMPatterns ; // FIXME: defm : BFMPatterns ; @@ -1622,8 +1610,6 @@ defm : IntMed3Pat; defm : IntMed3Pat; -} - // This matches 16 permutations of // max(min(x, y), min(max(x, y), z)) class FPMed3Pat { let isPseudo = 1; let isCodeGenOnly = 1; - let SubtargetPredicate = isGCN; let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -757,7 +755,6 @@ let Defs = [SCC]; let SchedRW = [WriteSALU]; let UseNamedOperandTable = 1; - let SubtargetPredicate = isGCN; } class SOPC_Base op, RegisterOperand rc0, RegisterOperand rc1, @@ -855,7 +852,6 @@ let SchedRW = [WriteSALU]; let UseNamedOperandTable = 1; - let SubtargetPredicate = isGCN; } Index: lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp =================================================================== --- lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -229,7 +229,8 @@ unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) { - if (!STI->getFeatureBits().test(FeatureGCN)) + assert(FlatWorkGroupSize != 0); + if (STI->getTargetTriple().getArch() != Triple::amdgcn) return 8; unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize); if (N == 1) Index: lib/Target/AMDGPU/VOP1Instructions.td =================================================================== --- lib/Target/AMDGPU/VOP1Instructions.td +++ lib/Target/AMDGPU/VOP1Instructions.td @@ -47,7 +47,6 @@ let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let SubtargetPredicate = isGCN; let VOP1 = 1; let VALU = 1; @@ -155,7 +154,6 @@ let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let SubtargetPredicate = isGCN; let VOP1 = 1; let VALU = 1; Index: lib/Target/AMDGPU/VOP2Instructions.td =================================================================== --- lib/Target/AMDGPU/VOP2Instructions.td +++ lib/Target/AMDGPU/VOP2Instructions.td @@ -68,7 +68,6 @@ let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let SubtargetPredicate = isGCN; let VOP2 = 1; let VALU = 1; @@ -392,8 +391,6 @@ // VOP2 Instructions //===----------------------------------------------------------------------===// -let SubtargetPredicate = isGCN, Predicates = [isGCN] in { - defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>; def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>; @@ -471,7 +468,6 @@ defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT, AMDGPUpk_u16_u32>; defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT, AMDGPUpk_i16_i32>; -} // End SubtargetPredicate = isGCN, Predicates = [isGCN] def : GCNPat< (AMDGPUadde i32:$src0, i32:$src1, i1:$src2), Index: lib/Target/AMDGPU/VOPCInstructions.td =================================================================== --- lib/Target/AMDGPU/VOPCInstructions.td +++ lib/Target/AMDGPU/VOPCInstructions.td @@ -82,8 +82,6 @@ let Uses = [EXEC]; let Defs = [VCC]; - let SubtargetPredicate = isGCN; - VOPProfile Pfl = P; } Index: lib/Target/AMDGPU/VOPInstructions.td =================================================================== --- lib/Target/AMDGPU/VOPInstructions.td +++ lib/Target/AMDGPU/VOPInstructions.td @@ -99,7 +99,6 @@ let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let SubtargetPredicate = isGCN; // Because SGPRs may be allowed if there are multiple operands, we // need a post-isel hook to insert copies in order to avoid Index: test/CodeGen/AMDGPU/memory-legalizer-mesa3d.ll =================================================================== --- test/CodeGen/AMDGPU/memory-legalizer-mesa3d.ll +++ test/CodeGen/AMDGPU/memory-legalizer-mesa3d.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s ; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s -; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx800 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s +; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s ; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s ; FUNC-LABEL: {{^}}system_acquire: