Index: lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
--- lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2542,6 +2542,7 @@
     return true;
   case ARM::CMPrr:
   case ARM::t2CMPrr:
+  case ARM::tCMPr:
     SrcReg = MI.getOperand(0).getReg();
     SrcReg2 = MI.getOperand(1).getReg();
     CmpMask = ~0;
@@ -2619,24 +2620,33 @@
 inline static bool isRedundantFlagInstr(const MachineInstr *CmpI,
                                         unsigned SrcReg, unsigned SrcReg2,
                                         int ImmValue, const MachineInstr *OI) {
-  if ((CmpI->getOpcode() == ARM::CMPrr ||
-       CmpI->getOpcode() == ARM::t2CMPrr) &&
-      (OI->getOpcode() == ARM::SUBrr ||
-       OI->getOpcode() == ARM::t2SUBrr) &&
+  if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) &&
+      (OI->getOpcode() == ARM::SUBrr || OI->getOpcode() == ARM::t2SUBrr) &&
       ((OI->getOperand(1).getReg() == SrcReg &&
         OI->getOperand(2).getReg() == SrcReg2) ||
        (OI->getOperand(1).getReg() == SrcReg2 &&
         OI->getOperand(2).getReg() == SrcReg)))
     return true;
 
-  if ((CmpI->getOpcode() == ARM::CMPri ||
-       CmpI->getOpcode() == ARM::t2CMPri) &&
-      (OI->getOpcode() == ARM::SUBri ||
-       OI->getOpcode() == ARM::t2SUBri) &&
+  if (CmpI->getOpcode() == ARM::tCMPr && OI->getOpcode() == ARM::tSUBrr &&
+      ((OI->getOperand(2).getReg() == SrcReg &&
+        OI->getOperand(3).getReg() == SrcReg2) ||
+       (OI->getOperand(2).getReg() == SrcReg2 &&
+        OI->getOperand(3).getReg() == SrcReg)))
+    return true;
+
+  if ((CmpI->getOpcode() == ARM::CMPri || CmpI->getOpcode() == ARM::t2CMPri) &&
+      (OI->getOpcode() == ARM::SUBri || OI->getOpcode() == ARM::t2SUBri) &&
       OI->getOperand(1).getReg() == SrcReg &&
       OI->getOperand(2).getImm() == ImmValue)
     return true;
 
+  if (CmpI->getOpcode() == ARM::tCMPi8 &&
+      (OI->getOpcode() == ARM::tSUBi8 || OI->getOpcode() == ARM::tSUBi3) &&
+      OI->getOperand(2).getReg() == SrcReg &&
+      OI->getOperand(3).getImm() == ImmValue)
+    return true;
+
   if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) &&
       (OI->getOpcode() == ARM::ADDrr || OI->getOpcode() == ARM::t2ADDrr ||
        OI->getOpcode() == ARM::ADDri || OI->getOpcode() == ARM::t2ADDri) &&
@@ -2644,6 +2654,14 @@
       OI->getOperand(0).getReg() == SrcReg &&
       OI->getOperand(1).getReg() == SrcReg2)
     return true;
+
+  if (CmpI->getOpcode() == ARM::tCMPr &&
+      (OI->getOpcode() == ARM::tADDi3 || OI->getOpcode() == ARM::tADDi8) &&
+      OI->getOperand(0).isReg() && OI->getOperand(2).isReg() &&
+      OI->getOperand(0).getReg() == SrcReg &&
+      OI->getOperand(2).getReg() == SrcReg2)
+    return true;
+
   return false;
 }
 
@@ -2760,7 +2778,8 @@
     // For CMPri w/ CmpValue != 0, a SubAdd may still be a candidate.
     // Thus we cannot return here.
     if (CmpInstr.getOpcode() == ARM::CMPri ||
-        CmpInstr.getOpcode() == ARM::t2CMPri)
+        CmpInstr.getOpcode() == ARM::t2CMPri ||
+        CmpInstr.getOpcode() == ARM::tCMPi8)
       MI = nullptr;
     else
       return false;
@@ -2898,7 +2917,9 @@
         // operands will be modified.
         unsigned Opc = SubAdd->getOpcode();
         bool IsSub = Opc == ARM::SUBrr || Opc == ARM::t2SUBrr ||
-                     Opc == ARM::SUBri || Opc == ARM::t2SUBri;
+                     Opc == ARM::SUBri || Opc == ARM::t2SUBri ||
+                     Opc == ARM::tSUBrr || Opc == ARM::tSUBi3 ||
+                     Opc == ARM::tSUBi8;
         if (!IsSub || (SrcReg2 != 0 && SubAdd->getOperand(1).getReg() == SrcReg2 &&
                        SubAdd->getOperand(2).getReg() == SrcReg)) {
           // VSel doesn't support condition code update.
Index: test/CodeGen/Thumb/peephole-cmp.mir
===================================================================
--- test/CodeGen/Thumb/peephole-cmp.mir
+++ test/CodeGen/Thumb/peephole-cmp.mir
@@ -58,9 +58,8 @@
 body:             |
   ; CHECK-LABEL: name: test1
   ; CHECK:      [[COPY:%[0-9]+]]:tgpr = COPY $r0
-  ; CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDi3 [[COPY]], 1, 14, $noreg
-  ; CHECK-NEXT: tCMPr killed [[ADD]], [[COPY]], 14, $noreg, implicit-def $cpsr
-  ; CHECK-NEXT: tBcc %bb.2, 3, $cpsr
+  ; CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDi3 [[COPY]], 1, 14, def $cpsr
+  ; CHECK-NEXT: tBcc %bb.2, 2, $cpsr
   bb.0 (%ir-block.0):
     successors: %bb.2(0x40000000), %bb.1(0x40000000)
     liveins: $r0
@@ -96,8 +95,7 @@
   ; CHECK-LABEL: name: test2
   ; CHECK:      [[COPY1:%[0-9]+]]:tgpr = COPY $r1
   ; CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0
-  ; CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBrr [[COPY0]], [[COPY1]], 14, $noreg
-  ; CHECK-NEXT: tCMPr [[COPY0]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+  ; CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBrr [[COPY0]], [[COPY1]], 14, def $cpsr
   ; CHECK-NEXT: tBcc %bb.2, 3, $cpsr
   bb.0 (%ir-block.0):
     successors: %bb.2(0x40000000), %bb.1(0x40000000)
@@ -132,8 +130,7 @@
 body:             |
   ; CHECK-LABEL: name: test3
   ; CHECK:      [[COPY:%[0-9]+]]:tgpr = COPY $r0
-  ; CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBi3 [[COPY]], 1, 14, $noreg
-  ; CHECK-NEXT: tCMPi8 [[COPY0]], 1, 14, $noreg, implicit-def $cpsr
+  ; CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBi3 [[COPY]], 1, 14, def $cpsr
   ; CHECK-NEXT: tBcc %bb.2, 3, $cpsr
   bb.0 (%ir-block.0):
     successors: %bb.2(0x40000000), %bb.1(0x40000000)