Index: lib/Target/AArch64/AArch64LegalizerInfo.cpp =================================================================== --- lib/Target/AArch64/AArch64LegalizerInfo.cpp +++ lib/Target/AArch64/AArch64LegalizerInfo.cpp @@ -272,9 +272,9 @@ // FP conversions getActionDefinitionsBuilder(G_FPTRUNC).legalFor( - {{s16, s32}, {s16, s64}, {s32, s64}}); + {{s16, s32}, {s16, s64}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}}); getActionDefinitionsBuilder(G_FPEXT).legalFor( - {{s32, s16}, {s64, s16}, {s64, s32}}); + {{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}}); // Conversions getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) Index: test/CodeGen/AArch64/GlobalISel/select-vector-fpconvert.ll =================================================================== --- /dev/null +++ test/CodeGen/AArch64/GlobalISel/select-vector-fpconvert.ll @@ -0,0 +1,29 @@ +; RUN: llc -mtriple=aarch64-unknown-unknown -global-isel -O0 %s -o - | FileCheck %s + +define <4 x float> @v4s16_to_v4s32(<4 x half> %a) { + ; CHECK-LABEL: v4s16_to_v4s32 + ; CHECK: fcvtl v0.4s, v0.4h + %1 = fpext <4 x half> %a to <4 x float> + ret <4 x float> %1 +} + +define <4 x half> @v4s32_to_v4s16(<4 x float> %a) { + ; CHECK-LABEL: v4s32_to_v4s16 + ; CHECK: fcvtn v0.4h, v0.4s + %1 = fptrunc <4 x float> %a to <4 x half> + ret <4 x half> %1 +} + +define <2 x double> @v2s32_to_v2s64(<2 x float> %a) { + ; CHECK-LABEL: v2s32_to_v2s64 + ; CHECK: fcvtl v0.2d, v0.2s + %1 = fpext <2 x float> %a to <2 x double> + ret <2 x double> %1 +} + +define <2 x float> @v2s64_to_v2s32(<2 x double> %a) { + ; CHECK-LABEL: v2s64_to_v2s32 + ; CHECK: fcvtn v0.2s, v0.2d + %1 = fptrunc <2 x double> %a to <2 x float> + ret <2 x float> %1 +} Index: test/CodeGen/AArch64/arm64-vcvt_f.ll =================================================================== --- test/CodeGen/AArch64/arm64-vcvt_f.ll +++ test/CodeGen/AArch64/arm64-vcvt_f.ll @@ -1,39 +1,61 @@ ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -O0 -fast-isel -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s +; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* \ +; RUN: -mtriple=arm64-eabi -aarch64-neon-syntax=apple \ +; RUN: | FileCheck %s --check-prefixes=GISEL,FALLBACK +; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_f64_f32) +; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_f64_f32) define <2 x double> @test_vcvt_f64_f32(<2 x float> %x) nounwind readnone ssp { ; CHECK-LABEL: test_vcvt_f64_f32: +; GISEL-LABEL: test_vcvt_f64_f32: %vcvt1.i = fpext <2 x float> %x to <2 x double> ; CHECK: fcvtl v0.2d, v0.2s +; GISEL: fcvtl v0.2d, v0.2s ret <2 x double> %vcvt1.i ; CHECK: ret +; GISEL: ret } +; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_high_f64_f32) +; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_high_f64_f32) define <2 x double> @test_vcvt_high_f64_f32(<4 x float> %x) nounwind readnone ssp { ; CHECK-LABEL: test_vcvt_high_f64_f32: +; GISEL-LABEL: test_vcvt_high_f64_f32: %cvt_in = shufflevector <4 x float> %x, <4 x float> undef, <2 x i32> %vcvt1.i = fpext <2 x float> %cvt_in to <2 x double> ; CHECK: fcvtl2 v0.2d, v0.4s +; GISEL: fcvtl2 v0.2d, v0.4s ret <2 x double> %vcvt1.i ; CHECK: ret +; GISEL: ret } +; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_f32_f64) +; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_f32_f64) define <2 x float> @test_vcvt_f32_f64(<2 x double> %v) nounwind readnone ssp { ; CHECK-LABEL: test_vcvt_f32_f64: +; GISEL-LABEL: test_vcvt_f32_f64: %vcvt1.i = fptrunc <2 x double> %v to <2 x float> ; CHECK: fcvtn +; GISEL: fcvtn ret <2 x float> %vcvt1.i ; CHECK: ret +; GISEL: ret } +; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_high_f32_f64) +; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_high_f32_f64) define <4 x float> @test_vcvt_high_f32_f64(<2 x float> %x, <2 x double> %v) nounwind readnone ssp { ; CHECK-LABEL: test_vcvt_high_f32_f64: - +; GISEL-LABEL: test_vcvt_high_f32_f64: %cvt = fptrunc <2 x double> %v to <2 x float> %vcvt2.i = shufflevector <2 x float> %x, <2 x float> %cvt, <4 x i32> ; CHECK: fcvtn2 +; GISEL: fcvtn2 ret <4 x float> %vcvt2.i ; CHECK: ret +; GISEL: ret } define <2 x float> @test_vcvtx_f32_f64(<2 x double> %v) nounwind readnone ssp {