Index: llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
===================================================================
--- llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -307,7 +307,6 @@
   bool isImm() const override {
     return Kind == Immediate || Kind == Expression;
   }
-  bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
   bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
Index: llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
===================================================================
--- llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
+++ llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
@@ -49,7 +49,6 @@
                              raw_ostream &O, const char *Modifier = nullptr);
   void printATBitsAsHint(const MCInst *MI, unsigned OpNo, raw_ostream &O);
 
-  void printU1ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU3ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
Index: llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
===================================================================
--- llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
+++ llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
@@ -279,13 +279,6 @@
     O << "+";
 }
 
-void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
-                                       raw_ostream &O) {
-  unsigned int Value = MI->getOperand(OpNo).getImm();
-  assert(Value <= 1 && "Invalid u1imm argument!");
-  O << (unsigned int)Value;
-}
-
 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
                                        raw_ostream &O) {
   unsigned int Value = MI->getOperand(OpNo).getImm();
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -656,7 +656,7 @@
                            IIC_IntCompare>, isPPC64;
   let Interpretation64Bit = 1, isCodeGenOnly = 1 in
   def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF),
-                                (ins u1imm:$L, g8rc:$rA, g8rc:$rB),
+                                (ins i1imm:$L, g8rc:$rA, g8rc:$rB),
                                 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>,
                Requires<[IsISA3_0]>;
   def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF),
@@ -1442,7 +1442,7 @@
 
 class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
                    InstrItinClass itin, list<dag> pattern>
-  : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L),
+  : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, i1imm:$L),
                  !strconcat(opc, " $rA, $rB, $L"), itin, pattern>;
 
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -329,7 +329,7 @@
              [(set Ty:$vD, (IntID Ty:$vA))]>;
 
 class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
-  : VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, u1imm:$ST, u4imm:$SIX),
+  : VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, i1imm:$ST, u4imm:$SIX),
               !strconcat(opc, " $vD, $vA, $ST, $SIX"), IIC_VecFP,
               [(set Ty:$vD, (IntID Ty:$vA, imm:$ST, imm:$SIX))]>;
 
@@ -1453,7 +1453,7 @@
 // [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set.
 class VX_VT5_EO5_VB5_PS1_XO9_o<bits<5> eo, bits<9> xo, string opc,
                                list<dag> pattern>
-  : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB, u1imm:$PS),
+  : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB, i1imm:$PS),
                         !strconcat(opc, " $vD, $vB, $PS"), IIC_VecFP, pattern> {
   let Defs = [CR6];
 }
@@ -1484,7 +1484,7 @@
 // [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set.
 class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern>
   : VX_RD5_RSp5_PS1_XO9<xo,
-                   (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u1imm:$PS),
+                   (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, i1imm:$PS),
                    !strconcat(opc, " $vD, $vA, $vB, $PS"), IIC_VecFP, pattern> {
   let Defs = [CR6];
 }
Index: llvm/lib/Target/PowerPC/PPCInstrHTM.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrHTM.td
+++ llvm/lib/Target/PowerPC/PPCInstrHTM.td
@@ -27,10 +27,10 @@
 let Predicates = [HasHTM] in {
 
 def TBEGIN : XForm_htm0 <31, 654,
-                         (outs crrc0:$ret), (ins u1imm:$R), "tbegin. $R", IIC_SprMTSPR, []>;
+                         (outs crrc0:$ret), (ins i1imm:$R), "tbegin. $R", IIC_SprMTSPR, []>;
 
 def TEND : XForm_htm1 <31, 686,
-                       (outs crrc0:$ret), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR, []>;
+                       (outs crrc0:$ret), (ins i1imm:$A), "tend. $A", IIC_SprMTSPR, []>;
 
 def TABORT : XForm_base_r3xo <31, 910,
                               (outs crrc0:$ret), (ins gprc:$A), "tabort. $A", IIC_SprMTSPR,
@@ -60,7 +60,7 @@
                                  isDOT;
 
 def TSR : XForm_htm2 <31, 750,
-                      (outs crrc0:$ret), (ins u1imm:$L), "tsr. $L", IIC_SprMTSPR, []>,
+                      (outs crrc0:$ret), (ins i1imm:$L), "tsr. $L", IIC_SprMTSPR, []>,
                       isDOT;
 
 def TCHECK : XForm_htm3 <31, 718,
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -562,15 +562,6 @@
   let ParserMatchClass = PPCRegSPE4RCAsmOperand;
 }
 
-def PPCU1ImmAsmOperand : AsmOperandClass {
-  let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
-  let RenderMethod = "addImmOperands";
-}
-def u1imm   : Operand<i32> {
-  let PrintMethod = "printU1ImmOperand";
-  let ParserMatchClass = PPCU1ImmAsmOperand;
-}
-
 def PPCU2ImmAsmOperand : AsmOperandClass {
   let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
   let RenderMethod = "addImmOperands";
@@ -1594,7 +1585,7 @@
                                (PPCmfbhrbe imm:$imm, imm:$dmy))]>,
                          PPC970_DGroup_First;
 
-def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm",
+def RFEBB : XLForm_S<19, 146, (outs), (ins i1imm:$imm), "rfebb $imm",
                      IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
                      PPC970_DGroup_Single;
 
@@ -2243,7 +2234,7 @@
   def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
                            "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
   def CMPRB  : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF),
-                                (ins u1imm:$L, g8rc:$rA, g8rc:$rB),
+                                (ins i1imm:$L, g8rc:$rA, g8rc:$rB),
                                 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>,
                Requires<[IsISA3_0]>;
 }
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2658,7 +2658,7 @@
   class Z23_VT5_R1_VB5_RMC2_EX1<bits<6> opcode, bits<8> xo, bit ex, string opc,
                                 list<dag> pattern>
     : Z23Form_8<opcode, xo,
-                (outs vrrc:$vT), (ins u1imm:$r, vrrc:$vB, u2imm:$rmc),
+                (outs vrrc:$vT), (ins i1imm:$r, vrrc:$vB, u2imm:$rmc),
                 !strconcat(opc, " $r, $vT, $vB, $rmc"), IIC_VecFP, pattern> {
     let RC = ex;
   }