Index: llvm/trunk/include/llvm/MC/MCInstPrinter.h =================================================================== --- llvm/trunk/include/llvm/MC/MCInstPrinter.h +++ llvm/trunk/include/llvm/MC/MCInstPrinter.h @@ -64,6 +64,10 @@ virtual ~MCInstPrinter(); + /// Customize the printer according to a command line option. + /// @return true if the option is recognized and applied. + virtual bool applyTargetSpecificCLOption(StringRef Opt) { return false; } + /// Specify a stream to emit comments to. void setCommentStream(raw_ostream &OS) { CommentStream = &OS; } Index: llvm/trunk/include/llvm/Target/Target.td =================================================================== --- llvm/trunk/include/llvm/Target/Target.td +++ llvm/trunk/include/llvm/Target/Target.td @@ -121,6 +121,10 @@ // this register class when printing. class RegAltNameIndex { string Namespace = ""; + + // A set to be used if the name for a register is not defined in this set. + // This allows creating name sets with only a few alternative names. + RegAltNameIndex FallbackRegAltNameIndex = ?; } def NoRegAltName : RegAltNameIndex; Index: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td =================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td @@ -13,7 +13,8 @@ //===----------------------------------------------------------------------===// // Registers are identified with 4-bit ID numbers. -class ARMReg Enc, string n, list subregs = []> : Register { +class ARMReg Enc, string n, list subregs = [], + list altNames = []> : Register { let HWEncoding = Enc; let Namespace = "ARM"; let SubRegs = subregs; @@ -26,6 +27,11 @@ let Namespace = "ARM"; } +let Namespace = "ARM", + FallbackRegAltNameIndex = NoRegAltName in { + def RegNamesRaw : RegAltNameIndex; +} + // Subregister indices. let Namespace = "ARM" in { def qqsub_0 : SubRegIndex<256>; @@ -83,9 +89,11 @@ def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>; def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>; def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>; -def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>; -def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>; -def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>; +let RegAltNameIndices = [RegNamesRaw] in { +def SP : ARMReg<13, "sp", [], ["r13"]>, DwarfRegNum<[13]>; +def LR : ARMReg<14, "lr", [], ["r14"]>, DwarfRegNum<[14]>; +def PC : ARMReg<15, "pc", [], ["r15"]>, DwarfRegNum<[15]>; +} } // Float registers Index: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h =================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h @@ -13,6 +13,7 @@ #ifndef LLVM_LIB_TARGET_ARM_INSTPRINTER_ARMINSTPRINTER_H #define LLVM_LIB_TARGET_ARM_INSTPRINTER_ARMINSTPRINTER_H +#include "MCTargetDesc/ARMMCTargetDesc.h" #include "llvm/MC/MCInstPrinter.h" namespace llvm { @@ -22,6 +23,8 @@ ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI); + bool applyTargetSpecificCLOption(StringRef Opt) override; + void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override; void printRegName(raw_ostream &OS, unsigned RegNo) const override; @@ -35,7 +38,8 @@ unsigned PrintMethodIdx, const MCSubtargetInfo &STI, raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); + static const char *getRegisterName(unsigned RegNo, + unsigned AltIdx = ARM::NoRegAltName); void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); @@ -235,6 +239,9 @@ template void printComplexRotationOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O); + +private: + unsigned DefaultAltIdx = ARM::NoRegAltName; }; } // end namespace llvm Index: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -72,8 +72,20 @@ const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {} +bool ARMInstPrinter::applyTargetSpecificCLOption(StringRef Opt) { + if (Opt == "reg-names-std") { + DefaultAltIdx = ARM::NoRegAltName; + return true; + } + if (Opt == "reg-names-raw") { + DefaultAltIdx = ARM::RegNamesRaw; + return true; + } + return false; +} + void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { - OS << markup(""); + OS << markup(""); } void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, Index: llvm/trunk/test/tools/llvm-objdump/ARM/reg-names.s =================================================================== --- llvm/trunk/test/tools/llvm-objdump/ARM/reg-names.s +++ llvm/trunk/test/tools/llvm-objdump/ARM/reg-names.s @@ -0,0 +1,18 @@ +@ RUN: llvm-mc %s -triple armv5-unknown-linux -filetype=obj -o %t +@ RUN: llvm-objdump -d %t | FileCheck -check-prefix=STD %s +@ RUN: llvm-objdump -d -Mreg-names-std %t \ +@ RUN: | FileCheck -check-prefix=STD %s +@ RUN: llvm-objdump -d --disassembler-options=reg-names-raw %t \ +@ RUN: | FileCheck -check-prefix=RAW %s +@ RUN: llvm-objdump -d -Mreg-names-raw,reg-names-std %t \ +@ RUN: | FileCheck -check-prefix=STD %s +@ RUN: llvm-objdump -d -Mreg-names-std,reg-names-raw %t \ +@ RUN: | FileCheck -check-prefix=RAW %s +@ RUN: not llvm-objdump -d -Munknown %t 2>&1 \ +@ RUN: | FileCheck -check-prefix=ERR %s +@ ERR: Unrecognized disassembler option: unknown + +.text + add r13, r14, r15 +@ STD: add sp, lr, pc +@ RAW: add r13, r14, r15 Index: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp =================================================================== --- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp +++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp @@ -293,6 +293,15 @@ cl::NotHidden, cl::Grouping, cl::aliasopt(DisassembleZeroes)); +static cl::list + DisassemblerOptions("disassembler-options", + cl::desc("Pass target specific disassembler options"), + cl::value_desc("options"), cl::CommaSeparated); +static cl::alias + DisassemblerOptionsShort("M", cl::desc("Alias for --disassembler-options"), + cl::NotHidden, cl::Prefix, cl::CommaSeparated, + cl::aliasopt(DisassemblerOptions)); + static StringRef ToolName; typedef std::vector> SectionSymbolsTy; @@ -1473,6 +1482,10 @@ PrettyPrinter &PIP = selectPrettyPrinter(Triple(TripleName)); SourcePrinter SP(Obj, TheTarget->getName()); + for (StringRef Opt : DisassemblerOptions) + if (!IP->applyTargetSpecificCLOption(Opt)) + error("Unrecognized disassembler option: " + Opt); + disassembleObject(TheTarget, Obj, Ctx, DisAsm.get(), MIA.get(), IP.get(), STI.get(), PIP, SP, InlineRelocs); } Index: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp =================================================================== --- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp +++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp @@ -585,11 +585,20 @@ O << " case "; if (!Namespace.empty()) O << Namespace << "::"; - O << AltName << ":\n" - << " assert(*(AsmStrs" << AltName << "+RegAsmOffset" << AltName - << "[RegNo-1]) &&\n" - << " \"Invalid alt name index for register!\");\n" - << " return AsmStrs" << AltName << "+RegAsmOffset" << AltName + O << AltName << ":\n"; + if (R->isValueUnset("FallbackRegAltNameIndex")) + O << " assert(*(AsmStrs" << AltName << "+RegAsmOffset" << AltName + << "[RegNo-1]) &&\n" + << " \"Invalid alt name index for register!\");\n"; + else { + O << " if (!*(AsmStrs" << AltName << "+RegAsmOffset" << AltName + << "[RegNo-1]))\n" + << " return getRegisterName(RegNo, "; + if (!Namespace.empty()) + O << Namespace << "::"; + O << R->getValueAsDef("FallbackRegAltNameIndex")->getName() << ");\n"; + } + O << " return AsmStrs" << AltName << "+RegAsmOffset" << AltName << "[RegNo-1];\n"; } O << " }\n";