Index: lib/Target/Mips/MipsSEFrameLowering.cpp =================================================================== --- lib/Target/Mips/MipsSEFrameLowering.cpp +++ lib/Target/Mips/MipsSEFrameLowering.cpp @@ -325,6 +325,8 @@ // We re-use the same spill slot each time so that the stack frame doesn't // grow too much in functions with a large number of moves. int FI = MF.getInfo()->getMoveF64ViaSpillFI(RC2); + if (!Subtarget.isLittle()) + std::swap(LoReg, HiReg); TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, &TRI, 0); TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, &TRI, @@ -369,6 +371,7 @@ unsigned DstReg = I->getOperand(0).getReg(); unsigned SrcReg = I->getOperand(1).getReg(); unsigned N = I->getOperand(2).getImm(); + int64_t Offset = 4 * (Subtarget.isLittle() ? N : (1 - N)); // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are // the cases where mfhc1 is not available). 64-bit architectures and @@ -385,7 +388,7 @@ int FI = MF.getInfo()->getMoveF64ViaSpillFI(RC); TII.storeRegToStack(MBB, I, SrcReg, I->getOperand(1).isKill(), FI, RC, &TRI, 0); - TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, N * 4); + TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, Offset); return true; } Index: test/CodeGen/Mips/fp64a.ll =================================================================== --- test/CodeGen/Mips/fp64a.ll +++ test/CodeGen/Mips/fp64a.ll @@ -44,8 +44,8 @@ ; 32R2-FP64A-LE: ldc1 $f0, 0($sp) ; 32R2-FP64A-BE: addiu $sp, $sp, -8 -; 32R2-FP64A-BE: sw $5, 0($sp) -; 32R2-FP64A-BE: sw $4, 4($sp) +; 32R2-FP64A-BE: sw $4, 0($sp) +; 32R2-FP64A-BE: sw $5, 4($sp) ; 32R2-FP64A-BE: ldc1 $f0, 0($sp) ; 64-NO-FP64A: daddiu $sp, $sp, -64 @@ -69,8 +69,8 @@ ; 32R2-FP64A-LE: ldc1 $f0, 0($sp) ; 32R2-FP64A-BE: addiu $sp, $sp, -8 -; 32R2-FP64A-BE: sw $7, 0($sp) -; 32R2-FP64A-BE: sw $6, 4($sp) +; 32R2-FP64A-BE: sw $6, 0($sp) +; 32R2-FP64A-BE: sw $7, 4($sp) ; 32R2-FP64A-BE: ldc1 $f0, 0($sp) ; 64-NO-FP64A-NOT: daddiu $sp, $sp @@ -94,8 +94,8 @@ ; 32R2-FP64A-LE: ldc1 $f0, 0($sp) ; 32R2-FP64A-BE: addiu $sp, $sp, -8 -; 32R2-FP64A-BE: sw $7, 0($sp) -; 32R2-FP64A-BE: sw $6, 4($sp) +; 32R2-FP64A-BE: sw $6, 0($sp) +; 32R2-FP64A-BE: sw $7, 4($sp) ; 32R2-FP64A-BE: ldc1 $f0, 0($sp) ; 64-NO-FP64A-NOT: daddiu $sp, $sp @@ -119,8 +119,8 @@ ; 32R2-FP64A-LE: ldc1 $f0, 0($sp) ; 32R2-FP64A-BE: addiu $sp, $sp, -8 -; 32R2-FP64A-BE: sw $7, 0($sp) -; 32R2-FP64A-BE: sw $6, 4($sp) +; 32R2-FP64A-BE: sw $6, 0($sp) +; 32R2-FP64A-BE: sw $7, 4($sp) ; 32R2-FP64A-BE: ldc1 $f0, 0($sp) ; 64-NO-FP64A: daddiu $sp, $sp, -48 @@ -155,11 +155,11 @@ ; 32R2-FP64A-LE: sub.d $f0, $[[T0]], $[[T1]] ; 32R2-FP64A-BE: addiu $sp, $sp, -8 -; 32R2-FP64A-BE: sw $7, 0($sp) -; 32R2-FP64A-BE: sw $6, 4($sp) +; 32R2-FP64A-BE: sw $6, 0($sp) +; 32R2-FP64A-BE: sw $7, 4($sp) ; 32R2-FP64A-BE: ldc1 $[[T1:f[0-9]+]], 0($sp) -; 32R2-FP64A-BE: sw $5, 0($sp) -; 32R2-FP64A-BE: sw $4, 4($sp) +; 32R2-FP64A-BE: sw $4, 0($sp) +; 32R2-FP64A-BE: sw $5, 4($sp) ; 32R2-FP64A-BE: ldc1 $[[T0:f[0-9]+]], 0($sp) ; 32R2-FP64A-BE: sub.d $f0, $[[T0]], $[[T1]] @@ -188,10 +188,10 @@ ; 32R2-FP64A-BE: addiu $sp, $sp, -32 ; 32R2-FP64A-BE: sdc1 $f0, 16($sp) -; 32R2-FP64A-BE: lw $6, 20($sp) +; 32R2-FP64A-BE: lw $6, 16($sp) ; FIXME: This store is redundant ; 32R2-FP64A-BE: sdc1 $f0, 16($sp) -; 32R2-FP64A-BE: lw $7, 16($sp) +; 32R2-FP64A-BE: lw $7, 20($sp) ; 64-NO-FP64A: mov.d $f13, $f0 }