Index: lib/CodeGen/GlobalISel/LegalizerHelper.cpp =================================================================== --- lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -1204,6 +1204,7 @@ case TargetOpcode::G_FDIV: case TargetOpcode::G_FREM: case TargetOpcode::G_FCEIL: + case TargetOpcode::G_FFLOOR: case TargetOpcode::G_FCOS: case TargetOpcode::G_FSIN: case TargetOpcode::G_FLOG10: @@ -1852,6 +1853,7 @@ case G_FLOG2: case G_FLOG10: case G_FCEIL: + case G_FFLOOR: case G_INTRINSIC_ROUND: case G_INTRINSIC_TRUNC: case G_FCOS: Index: lib/Target/AArch64/AArch64LegalizerInfo.cpp =================================================================== --- lib/Target/AArch64/AArch64LegalizerInfo.cpp +++ lib/Target/AArch64/AArch64LegalizerInfo.cpp @@ -124,7 +124,7 @@ getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64}); - getActionDefinitionsBuilder({G_FCEIL, G_FABS, G_FSQRT}) + getActionDefinitionsBuilder({G_FCEIL, G_FABS, G_FSQRT, G_FFLOOR}) // If we don't have full FP16 support, then scalarize the elements of // vectors containing fp16 types. .fewerElementsIf( Index: lib/Target/AArch64/AArch64RegisterBankInfo.cpp =================================================================== --- lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -392,6 +392,7 @@ case TargetOpcode::G_FPEXT: case TargetOpcode::G_FPTRUNC: case TargetOpcode::G_FCEIL: + case TargetOpcode::G_FFLOOR: case TargetOpcode::G_FNEG: case TargetOpcode::G_FCOS: case TargetOpcode::G_FSIN: Index: test/CodeGen/AArch64/GlobalISel/select-floor.mir =================================================================== --- /dev/null +++ test/CodeGen/AArch64/GlobalISel/select-floor.mir @@ -0,0 +1,130 @@ +# RUN: llc -verify-machineinstrs -mtriple aarch64--- \ +# RUN: -run-pass=instruction-select -mattr=+fullfp16 -global-isel %s -o - \ +# RUN: | FileCheck %s +... +--- +name: floor_float +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +body: | + bb.0: + ; CHECK-LABEL: name: floor_float + ; CHECK: %{{[0-9]+}}:fpr32 = FRINTMSr %{{[0-9]+}} + liveins: $s0 + %0:fpr(s32) = COPY $s0 + %1:fpr(s32) = G_FFLOOR %0 + $s0 = COPY %1(s32) + +... +--- +name: floor_double +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +body: | + bb.0: + ; CHECK-LABEL: name: floor_double + ; CHECK: %{{[0-9]+}}:fpr64 = FRINTMDr %{{[0-9]+}} + liveins: $d0 + %0:fpr(s64) = COPY $d0 + %1:fpr(s64) = G_FFLOOR %0 + $d0 = COPY %1(s64) + +... +--- +name: floor_v2f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +body: | + bb.0: + ; CHECK-LABEL: name: floor_v2f32 + ; CHECK: %{{[0-9]+}}:fpr64 = FRINTMv2f32 %{{[0-9]+}} + liveins: $d0 + %0:fpr(<2 x s32>) = COPY $d0 + %1:fpr(<2 x s32>) = G_FFLOOR %0 + $d0 = COPY %1(<2 x s32>) + +... +--- +name: floor_v4f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +body: | + bb.0: + ; CHECK-LABEL: name: floor_v4f32 + ; CHECK: %{{[0-9]+}}:fpr128 = FRINTMv4f32 %{{[0-9]+}} + liveins: $q0 + %0:fpr(<4 x s32>) = COPY $q0 + %1:fpr(<4 x s32>) = G_FFLOOR %0 + $q0 = COPY %1(<4 x s32>) + +... +--- +name: floor_v2f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +body: | + bb.0: + ; CHECK-LABEL: name: floor_v2f64 + ; CHECK: %{{[0-9]+}}:fpr128 = FRINTMv2f64 %{{[0-9]+}} + liveins: $q0 + %0:fpr(<2 x s64>) = COPY $q0 + %1:fpr(<2 x s64>) = G_FFLOOR %0 + $q0 = COPY %1(<2 x s64>) + +... +--- +name: floor_v4f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +body: | + bb.0: + ; CHECK-LABEL: name: floor_v4f16 + ; CHECK: %{{[0-9]+}}:fpr64 = FRINTMv4f16 %{{[0-9]+}} + liveins: $d0 + %0:fpr(<4 x s16>) = COPY $d0 + %1:fpr(<4 x s16>) = G_FFLOOR %0 + $d0 = COPY %1(<4 x s16>) + +... +--- +name: floor_v8f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +body: | + bb.0: + ; CHECK-LABEL: name: floor_v8f16 + ; CHECK: %{{[0-9]+}}:fpr128 = FRINTMv8f16 %{{[0-9]+}} + liveins: $q0 + %0:fpr(<8 x s16>) = COPY $q0 + %1:fpr(<8 x s16>) = G_FFLOOR %0 + $q0 = COPY %1(<8 x s16>) + +... Index: test/CodeGen/AArch64/arm64-vfloatintrinsics.ll =================================================================== --- test/CodeGen/AArch64/arm64-vfloatintrinsics.ll +++ test/CodeGen/AArch64/arm64-vfloatintrinsics.ll @@ -141,12 +141,20 @@ %1 = call %v4f16 @llvm.fabs.v4f16(%v4f16 %a) ret %v4f16 %1 } + +; FALLBACK-NOT: remark{{.*}}test_v4f16.floor define %v4f16 @test_v4f16.floor(%v4f16 %a) { ; CHECK-LABEL: test_v4f16.floor: ; CHECK-NOFP16-COUNT-4: frintm s{{[0-9]+}}, s{{[0-9]+}} ; CHECK-FP16-NOT: fcvt ; CHECK-FP16: frintm.4h ; CHECK-FP16-NEXT: ret + + ; GISEL-LABEL: test_v4f16.floor: + ; GISEL-NOFP16-COUNT-4: frintm s{{[0-9]+}}, s{{[0-9]+}} + ; GISEL-FP16-NOT: fcvt + ; GISEL-FP16: frintm.4h + ; GISEL-FP16-NEXT: ret %1 = call %v4f16 @llvm.floor.v4f16(%v4f16 %a) ret %v4f16 %1 } @@ -342,12 +350,20 @@ %1 = call %v8f16 @llvm.fabs.v8f16(%v8f16 %a) ret %v8f16 %1 } + +; FALLBACK-NOT: remark{{.*}}test_v8f16.floor define %v8f16 @test_v8f16.floor(%v8f16 %a) { ; CHECK-LABEL: test_v8f16.floor: ; CHECK-NOFP16-COUNT-8: frintm s{{[0-9]+}}, s{{[0-9]+}} ; CHECK-FP16-NOT: fcvt ; CHECK-FP16: frintm.8h ; CHECK-FP16-NEXT: ret + + ; GISEL-LABEL: test_v8f16.floor: + ; GISEL-NOFP16-COUNT-8: frintm s{{[0-9]+}}, s{{[0-9]+}} + ; GISEL-FP16-NOT: fcvt + ; GISEL-FP16: frintm.8h + ; GISEL-FP16-NEXT: ret %1 = call %v8f16 @llvm.floor.v8f16(%v8f16 %a) ret %v8f16 %1 } @@ -516,9 +532,13 @@ %1 = call %v2f32 @llvm.fabs.v2f32(%v2f32 %a) ret %v2f32 %1 } + +; FALLBACK-NOT: remark{{.*}}test_v2f32.floor ; CHECK-LABEL: test_v2f32.floor: +; GISEL-LABEL: test_v2f32.floor: define %v2f32 @test_v2f32.floor(%v2f32 %a) { ; CHECK: frintm.2s + ; GISEL: frintm.2s %1 = call %v2f32 @llvm.floor.v2f32(%v2f32 %a) ret %v2f32 %1 } @@ -671,9 +691,13 @@ %1 = call %v4f32 @llvm.fabs.v4f32(%v4f32 %a) ret %v4f32 %1 } + +; FALLBACK-NOT: remark{{.*}}test_v4f32.floor ; CHECK: test_v4f32.floor: +; GISEL: test_v4f32.floor: define %v4f32 @test_v4f32.floor(%v4f32 %a) { ; CHECK: frintm.4s + ; GISEL frintm.4s %1 = call %v4f32 @llvm.floor.v4f32(%v4f32 %a) ret %v4f32 %1 } @@ -826,9 +850,13 @@ %1 = call %v2f64 @llvm.fabs.v2f64(%v2f64 %a) ret %v2f64 %1 } + +; FALLBACK-NOT: remark{{.*}}test_v2f64.floor ; CHECK: test_v2f64.floor: +; GISEL: test_v2f64.floor: define %v2f64 @test_v2f64.floor(%v2f64 %a) { ; CHECK: frintm.2d + ; GISEL: frintm.2d %1 = call %v2f64 @llvm.floor.v2f64(%v2f64 %a) ret %v2f64 %1 } Index: test/CodeGen/AArch64/f16-instructions.ll =================================================================== --- test/CodeGen/AArch64/f16-instructions.ll +++ test/CodeGen/AArch64/f16-instructions.ll @@ -1168,6 +1168,19 @@ ; CHECK-FP16-NEXT: frintm h0, h0 ; CHECK-FP16-NEXT: ret +; FALLBACK-NOT: remark:{{.*}}test_floor +; FALLBACK-FP16-NOT: remark:{{.*}}test_floor + +; GISEL-CVT-LABEL: test_floor: +; GISEL-CVT-NEXT: fcvt [[FLOAT32:s[0-9]+]], h0 +; GISEL-CVT-NEXT: frintm [[INT32:s[0-9]+]], [[FLOAT32]] +; GISEL-CVT-NEXT: fcvt h0, [[INT32]] +; GISEL-CVT-NEXT: ret + +; GISEL-FP16-LABEL: test_floor: +; GISEL-FP16-NEXT: frintm h0, h0 +; GISEL-FP16-NEXT: ret + define half @test_floor(half %a) #0 { %r = call half @llvm.floor.f16(half %a) ret half %r